TY  - JOUR
U1  - Zeitschriftenartikel, wissenschaftlich - begutachtet (reviewed)
A1  - Cadilha Marques, Gabriel
A1  - Birla, Anushka
A1  - Arnal Rus, August
A1  - Dehm, Simone
A1  - Ramon, Eloi
A1  - Tahoori, Mehdi Baradaran
A1  - Aghassi-Hagmann, Jasmin
T1  - Printed Logic Gates Based on Enhancement- and Depletion-Mode Electrolyte-Gated Transistors
JF  - IEEE Transactions on Electron Devices
N2  - Electrolyte-gated thin-film transistors (EGTs) with indium oxide channel, and expected lifetime of three months, enable low-voltage operation (~1 V) in the field of printed electronics (PEs). The channel width of our printed EGTs is varied between 200 and 1000 μm, whereas a channel length between 10 and 100 μm is used. Due to the lack of uniform performance p-type metal oxide semiconductors, n-type EGTs and passive elements are used to design circuits. For logic gates, transistor-resistor logic has been employed so far, but depletion and enhancement-mode EGTs in a transistor-transistor logic boost the circuit performance in terms of delay and signal swing. In this article, the threshold voltage of the EGT, which determines the operation mode, is tuned through sizing of the EGTs channel geometry. The feasibility of both transistor operation modes is demonstrated for logic gates and ring oscillators. An inverter operating at a supply voltage of 1 V shows a maximum gain of 9.6 and a propagation delay time of 0.7 ms, which represents an improvement of ~ 2x for the gain and oscillation frequency, in comparison with the resistor-transistor logic design. Moreover, the power consumption is reduced by 6x.
Y1  - 2020
SN  - 0018-9383 (Print)
SS  - 0018-9383 (Print)
SN  - 0096-2430 (Online)
SS  - 0096-2430 (Online)
U6  - https://doi.org/10.1109/TED.2020.3002208
DO  - https://doi.org/10.1109/TED.2020.3002208
VL  - 67
IS  - 8
SP  - 3146
EP  - 3151
ER  -