TY  - JOUR
U1  - Zeitschriftenartikel, wissenschaftlich - begutachtet (reviewed)
A1  - Ulianova, Veronika
A1  - Rasheed, Farhan
A1  - Bolat, Sami
A1  - Torres Sevilla, Galo
A1  - Didenko, Yurii
A1  - Feng, Xiaowei
A1  - Shorubalko, Ivan
A1  - Bachmann, Dominik
A1  - Tatarchuk, Dmytro
A1  - Tahoori, Mehdi Baradaran
A1  - Aghassi-Hagmann, Jasmin
A1  - Romanyuk, Yaroslav
T1  - Fabrication, Characterization and Simulation of Sputtered Pt/In-Ga-Zn-O Schottky Diodes for Low-Frequency Half-Wave Rectifier Circuit
JF  - IEEE Access
N2  - Amorphous In-Ga-Zn-O (IGZO) is a high-mobility semiconductor employed in modern thin-film transistors for displays and it is considered as a promising material for Schottky diode-based rectifiers. Properties of the electronic components based on IGZO strongly depend on the manufacturing parameters such as the oxygen partial pressure during IGZO sputtering and post-deposition thermal annealing. In this study, we investigate the combined effect of sputtering conditions of amorphous IGZO (In:Ga:Zn=1:1:1) and post-deposition thermal annealing on the properties of vertical thin-film Pt-IGZO-Cu Schottky diodes, and evaluated the applicability of the fabricated Schottky diodes for low-frequency half-wave rectifier circuits. The change of the oxygen content in the gas mixture from 1.64% to 6.25%, and post-deposition annealing is shown to increase the current rectification ratio from 10 5 to 10 7 at ±1 V, Schottky barrier height from 0.64 eV to 0.75 eV, and the ideality factor from 1.11 to 1.39. Half-wave rectifier circuits based on the fabricated Schottky diodes were simulated using parameters extracted from measured current-voltage and capacitance-voltage characteristics. The half-wave rectifier circuits were realized at 100 kHz and 300 kHz on as-fabricated Schottky diodes with active area of 200 μm × 200 μm, which is relevant for the near-field communication (125 kHz - 134 kHz), and provided the output voltage amplitude of 0.87 V for 2 V supply voltage. The simulation results matched with the measurement data, verifying the model accuracy for circuit level simulation.
Y1  - 2020
SN  - 2169-3536
SS  - 2169-3536
U6  - https://doi.org/10.1109/ACCESS.2020.3002267
DO  - https://doi.org/10.1109/ACCESS.2020.3002267
VL  - 8
SP  - 111783
EP  - 111790
ER  -