TY - JOUR U1 - Zeitschriftenartikel, wissenschaftlich - begutachtet (reviewed) A1 - Erozan, Ahmet Turan A1 - Cadilha Marques, Gabriel A1 - Golanbari, Mohammad Saber A1 - Bishnoi, Rajendra A1 - Dehm, Simone A1 - Aghassi-Hagmann, Jasmin A1 - Tahoori, Mehdi Baradaran T1 - Inkjet-Printed EGFET-Based Physical Unclonable Function-Design, Evaluation, and Fabrication JF - IEEE transactions on very large scale integration (VLSI) systems Y1 - 2018 U6 - https://dx.doi.org/10.1109/TVLSI.2018.2866188 DO - https://dx.doi.org/10.1109/TVLSI.2018.2866188 VL - 26 IS - 12 SP - 2935 EP - 2946 ER - TY - JOUR U1 - Zeitschriftenartikel, wissenschaftlich - begutachtet (reviewed) A1 - Erozan, Ahmet Turan A1 - Hefenbrock, Michael A1 - Beigl, Michael A1 - Aghassi-Hagmann, Jasmin A1 - Tahoori, Mehdi Baradaran T1 - Reverse Engineering of Printed Electronics Circuits: From Imaging to Netlist Extraction JF - IEEE Transactions on Information Forensics and Security N2 - Printed electronics (PE) circuits have several advantages over silicon counterparts for the applications where mechanical flexibility, extremely low-cost, large area, and custom fabrication are required. The custom (personalized) fabrication is a key feature of this technology, enabling customization per application, even in small quantities due to low-cost printing compared with lithography. However, the personalized and on-demand fabrication, the non-standard circuit design, and the limited number of printing layers with larger geometries compared with traditional silicon chip manufacturing open doors for new and unique reverse engineering (RE) schemes for this technology. In this paper, we present a robust RE methodology based on supervised machine learning, starting from image acquisition all the way to netlist extraction. The results show that the proposed RE methodology can reverse engineer the PE circuits with very limited manual effort and is robust against non-standard circuit design, customized layouts, and high variations resulting from the inherent properties of PE manufacturing processes. Y1 - 2019 SN - 1556-6013 (Print) SS - 1556-6013 (Print) SN - 1556-6021 (Online) SS - 1556-6021 (Online) U6 - https://dx.doi.org/10.1109/TIFS.2019.2922237 DO - https://dx.doi.org/10.1109/TIFS.2019.2922237 VL - 15 SP - 475 EP - 486 PB - IEEE CY - New York ER - TY - JOUR U1 - Zeitschriftenartikel, wissenschaftlich - begutachtet (reviewed) A1 - Cadilha Marques, Gabriel A1 - Weller, Dennis D. A1 - Erozan, Ahmet Turan A1 - Feng, Xiaowei A1 - Tahoori, Mehdi Baradaran A1 - Aghassi-Hagmann, Jasmin T1 - Progress Report on "From Printed Electrolyte‐Gated Metal‐Oxide Devices to Circuits" JF - Advanced Materials. Special Issue: Materials Research at Karlsruhe Institute of Technology N2 - Printed electrolyte-gated oxide electronics is an emerging electronic technology in the low voltage regime (≤1 V). Whereas in the past mainly dielectrics have been used for gating the transistors, many recent approaches employ the advantages of solution processable, solid polymer electrolytes, or ion gels that provide high gate capacitances produced by a Helmholtz double layer, allowing for low-voltage operation. Herein, with special focus on work performed at KIT recent advances in building electronic circuits based on indium oxide, n-type electrolyte-gated field-effect transistors (EGFETs) are reviewed. When integrated into ring oscillator circuits a digital performance ranging from 250 Hz at 1 V up to 1 kHz is achieved. Sequential circuits such as memory cells are also demonstrated. More complex circuits are feasible but remain challenging also because of the high variability of the printed devices. However, the device inherent variability can be even exploited in security circuits such as physically unclonable functions (PUFs), which output a reliable and unique, device specific, digital response signal. As an overall advantage of the technology all the presented circuits can operate at very low supply voltages (0.6 V), which is crucial for low-power printed electronics applications. Y1 - 2019 SN - 0935-9648 (Print) SS - 0935-9648 (Print) SN - 1521-4095 (Online) SS - 1521-4095 (Online) U6 - https://dx.doi.org/10.1002/adma.201806483 DO - https://dx.doi.org/10.1002/adma.201806483 VL - 31 IS - 26 SP - 1806483 S1 - 9 PB - Wiley CY - Weinheim ER - TY - JOUR U1 - Zeitschriftenartikel, wissenschaftlich - begutachtet (reviewed) A1 - Erozan, Ahmet Turan A1 - Wang, Guan Ying A1 - Bishnoi, Rajendra A1 - Aghassi-Hagmann, Jasmin A1 - Tahoori, Mehdi Baradaran T1 - A Compact Low-Voltage True Random Number Generator based on Inkjet Printing Technology JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems N2 - Printed electronics (PE) is a fast-growing field with promising applications in wearables, smart sensors, and smart cards, since it provides mechanical flexibility, and low-cost, on-demand, and customizable fabrication. To secure the operation of these applications, true random number generators (TRNGs) are required to generate unpredictable bits for cryptographic functions and padding. However, since the additive fabrication process of the PE circuits results in high intrinsic variations due to the random dispersion of the printed inks on the substrate, constructing a printed TRNG is challenging. In this article, we exploit the additive customizable fabrication feature of inkjet printing to design a TRNG based on electrolyte-gated field-effect transistors (EGFETs). We also propose a printed resistor tuning flow for the TRNG circuit to mitigate the overall process variation of the TRNG so that the generated bits are mostly based on the random noise in the circuit, providing a true random behavior. The simulation results show that the overall process variation of the TRNGs is mitigated by 110 times, and the generated bitstream of the tuned TRNGs passes the National Institute of Standards and Technology - Statistical Test Suite. For the proof of concept, the proposed TRNG circuit was fabricated and tuned. The characterization results of the tuned TRNGs prove that the TRNGs generate random bitstreams at the supply voltage of down to 0.5 V. Hence, the proposed TRNG design is suitable to secure low-power applications in this domain. Y1 - 2020 SN - 1063-8210 (Print) SS - 1063-8210 (Print) SN - 1557-9999 (Online) SS - 1557-9999 (Online) U6 - https://dx.doi.org/10.1109/TVLSI.2020.2975876 DO - https://dx.doi.org/10.1109/TVLSI.2020.2975876 VL - 28 IS - 6 SP - 1485 EP - 1495 ER - TY - JOUR U1 - Zeitschriftenartikel, wissenschaftlich - begutachtet (reviewed) A1 - Erozan, Ahmet Turan A1 - Weller, Dennis D. A1 - Feng, Yijing A1 - Cadilha Marques, Gabriel A1 - Aghassi-Hagmann, Jasmin A1 - Tahoori, Mehdi Baradaran T1 - A Printed Camouflaged Cell against Reverse Engineering of Printed Electronics Circuits JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems N2 - Printed electronics (PE) enables disruptive applications in wearables, smart sensors, and healthcare since it provides mechanical flexibility, low cost, and on-demand fabrication. The progress in PE raises trust issues in the supply chain and vulnerability to reverse engineering (RE) attacks. Recently, RE attacks on PE circuits have been successfully performed, pointing out the need for countermeasures against RE, such as camouflaging. In this article, we propose a printed camouflaged logic cell that can be inserted into PE circuits to thwart RE. The proposed cell is based on three components achieved by changing the fabrication process that exploits the additive manufacturing feature of PE. These components are optically look-alike, while their electrical behaviors are different, functioning as a transistor, short, and open. The properties of the proposed cell and standard PE cells are compared in terms of voltage swing, delay, power consumption, and area. Moreover, the proposed camouflaged cell is fabricated and characterized to prove its functionality. Furthermore, numerous camouflaged components are fabricated, and their (in)distinguishability is assessed to validate their optical similarities based on the recent RE attacks on PE. The results show that the proposed cell is a promising candidate to be utilized in camouflaging PE circuits with negligible overhead. Y1 - 2020 SN - 1063-8210 (Print) SS - 1063-8210 (Print) SN - 1557-9999 (Online) SS - 1557-9999 (Online) U6 - https://dx.doi.org/10.1109/TVLSI.2020.3022776 DO - https://dx.doi.org/10.1109/TVLSI.2020.3022776 VL - 28 IS - 11 SP - 2448 EP - 2458 ER - TY - JOUR U1 - Zeitschriftenartikel, wissenschaftlich - begutachtet (reviewed) A1 - Erozan, Ahmet Turan A1 - Weller, Dennis D. A1 - Rasheed, Farhan A1 - Bishnoi, Rajendra A1 - Aghassi-Hagmann, Jasmin A1 - Tahoori, Mehdi Baradaran T1 - A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems N2 - Advances in printed electronics (PE) enables new applications, particularly in ultra-low-cost domains. However, achieving high-throughput printing processes and manufacturing yield is one of the major challenges in the large-scale integration of PE technology. In this article, we present a programmable printed circuit based on an efficient printed lookup table (pLUT) to address these challenges by combining the advantages of the high-throughput advanced printing and maskless point-of-use final configuration printing. We propose a novel pLUT design which is more efficient in PE realization compared to existing LUT designs. The proposed pLUT design is simulated, fabricated, and programmed as different logic functions with inkjet printed conductive ink to prove that it can realize digital circuit functionality with the use of programmability features. The measurements show that the fabricated LUT design is operable at 1 V. Y1 - 2020 SN - 1063-8210 (Print) SS - 1063-8210 (Print) SN - 1557-9999 (Online) SS - 1557-9999 (Online) U6 - https://dx.doi.org/10.1109/TVLSI.2020.2980931 DO - https://dx.doi.org/10.1109/TVLSI.2020.2980931 VL - 28 IS - 6 SP - 1496 EP - 1504 ER -