Bayesian Optimized Mixture Importance Sampling for High-Sigma Failure Rate Estimation

  • In many application domains, in particular automotives, guaranteeing a very low failure rate is crucial to meet functional and safety standards. Especially, reliable operation of memory components such as SRAM cells is of essential importance. Due to aggressive technology downscaling, process and runtime variations significantly impact manufacturing yield as well as functionality. For this reason,In many application domains, in particular automotives, guaranteeing a very low failure rate is crucial to meet functional and safety standards. Especially, reliable operation of memory components such as SRAM cells is of essential importance. Due to aggressive technology downscaling, process and runtime variations significantly impact manufacturing yield as well as functionality. For this reason, a thorough memory failure rate assessment is imperative for correct circuit operation and yield improvement. In this regard, Monte Carlo simulations have been used as the conventional method to estimate the variability induced failure rate of memory components. However, Monte Carlo methods become infeasible when estimating rare events such as high-sigma failure rates. To this end, Importance Sampling methods have been proposed which reduce the number of required simulations substantially. However, existing methods still suffer from inaccuracies and high computational efforts, in particular for high-sigma problems. In this paper, we fill this gap by presenting an efficient mixture Importance Sampling approach based on Bayesian optimization, which deploys a surface model of the objective function to find the most probable failure points. Its advantages include constant complexity independent of the dimensions of design space, the potential to find the global extrema, and higher trustworthiness of the estimated failure rate by accurately exploring the design space. The approach is evaluated on a 6T-SRAM cell as well as a master-slave latch based on a 28nm FDSOI process. The results show an improvement in accuracy, resulting in up to 63× better accuracy in estimating failure rates compared to the best state-of-the-art solutions on a 28nm technology node.show moreshow less

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Metadaten
Author:Dennis D. Weller, Michael Hefenbrock, Mohammad Saber Golanbari, Michael Beigl, Jasmin Aghassi-HagmannORCiDGND, Mehdi Baradaran Tahoori
Creating Corporation:IEEE
Year of Publication:2019
Language:English
Parent Title (English):IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISSN:0278-0070 (Print)
ISSN:1937-4151 (Online)
First Page:1
Last Page:11
Document Type:Article (reviewed)
Institutes:Hochschule Offenburg / Bibliografie
Acces Right:Zugriffsbeschränkt
Release Date:2020/01/23
Licence (German):License LogoEs gilt das UrhG
DOI:https://doi.org/10.1109/TCAD.2019.2961321