Design and Test of a Gigabit Ethernet MAC for High-Speed HIL-Support

  • The efficient support of Hardwae-In-theLoop (HIL) in the design process of hardwaresoftware-co-designed systems is an ongoing challenge. This paper presents a network-based integration of hardware elements into the softwarebased image processing tool „ADTF“, based on a high-performance Gigabit Ethernet MAC and a highly-efficient TCP/IP-stack. The MAC has been designed in VHDL. It was verified in aThe efficient support of Hardwae-In-theLoop (HIL) in the design process of hardwaresoftware-co-designed systems is an ongoing challenge. This paper presents a network-based integration of hardware elements into the softwarebased image processing tool „ADTF“, based on a high-performance Gigabit Ethernet MAC and a highly-efficient TCP/IP-stack. The MAC has been designed in VHDL. It was verified in a SystemCsimulation environment and tested on several Altera FPGAs.show moreshow less

Export metadata

Additional Services

Share in Twitter Search Google Scholar
Metadaten
Author:Alexander Rohleder, Steffen Jäckel, Axel Sikora
Publisher:Hochschule Ulm
Place of publication:Ulm
Year of Publication:2011
Language:English
Parent Title (German):Tagungsband zum Workshop der Multiprojekt-Chip-Gruppe Baden-Württemberg, Furtwangen, Juli 2011
Volume:46
ISSN:1682-9221
First Page:35
Last Page:40
Document Type:Conference Proceeding
Institutes:Hochschule Offenburg / Bibliografie
Release Date:2015/06/13
Licence (German):License LogoEs gilt das UrhG
URL:https://www.mpc-gruppe.de/de/workshopbaende.html
URL:https://www.strategiekreis-automobile-zukunft.de/public/projekte/propedes/dokumente/mpc_46_paper_110920.pdf