Specification and Implementation of an AXI4-Burst-Master
- Due to the ever increasing complexity of system-on-chip solutions, more and more complex modules can be monolithically integrated, such as CPU cores, memories, and interface controllers. Increasingly powerful bus systems connect these modules. This paper presents the implementation of a bus master, which is based on the AXI4 protocol. It is used for the system integration of a Gigabit EthernetDue to the ever increasing complexity of system-on-chip solutions, more and more complex modules can be monolithically integrated, such as CPU cores, memories, and interface controllers. Increasingly powerful bus systems connect these modules. This paper presents the implementation of a bus master, which is based on the AXI4 protocol. It is used for the system integration of a Gigabit Ethernet MAC-controller. It was designed in VHDL and tested in a SystemC-based simulation environment.…


| Document Type: | Conference Proceeding |
|---|---|
| Conference Type: | Konferenzartikel |
| Zitierlink: | https://opus.hs-offenburg.de/9053 | Bibliografische Angaben |
| Title (English): | Specification and Implementation of an AXI4-Burst-Master |
| Conference: | Workshop der Multiprojekt Chip-Gruppe Baden-Württemberg (50. : Juli 2013 : Konstanz) |
| Author: | Guy Christian Ngamy Nya GND, Steffen Jaeckel, Axel SikoraStaff MemberORCiDGND |
| Year of Publication: | 2013 |
| Creating Corporation: | Hochschule Ulm |
| Contributing Corporation / Conference: | MPC-Gruppe |
| First Page: | 59 |
| Last Page: | 64 |
| Parent Title (English): | MPC-Workshop Juli 2013 |
| Volume: | 50 |
| ISSN: | 1868-9221 |
| URL: | https://nbn-resolving.org/urn:nbn:de:bsz:ofb1-opus4-60330 |
| Language: | English | Inhaltliche Informationen |
| Institutes: | Fakultät Elektrotechnik und Informationstechnik (E+I) (bis 03/2019) |
| Collections of the Offenburg University: | Bibliografie |
| Journals: | Tagungsband zum Workshop der Multiprojekt Chip-Gruppe Baden-Württemberg |
| Tag: | AXI4-Master; Gigabit Ethernet MAC; SystemC; VHDL | Formale Angaben |
| Open Access: | Open Access |
| Bronze | |
| Licence (German): | Urheberrechtlich geschützt |




