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Design and Test of a Gigabit Ethernet MAC for High-Speed HIL-Support

  • The efficient support of Hardwae-In-theLoop (HIL) in the design process of hardwaresoftware-co-designed systems is an ongoing challenge. This paper presents a network-based integration of hardware elements into the softwarebased image processing tool „ADTF“, based on a high-performance Gigabit Ethernet MAC and a highly-efficient TCP/IP-stack. The MAC has been designed in VHDL. It was verified in aThe efficient support of Hardwae-In-theLoop (HIL) in the design process of hardwaresoftware-co-designed systems is an ongoing challenge. This paper presents a network-based integration of hardware elements into the softwarebased image processing tool „ADTF“, based on a high-performance Gigabit Ethernet MAC and a highly-efficient TCP/IP-stack. The MAC has been designed in VHDL. It was verified in a SystemCsimulation environment and tested on several Altera FPGAs.show moreshow less

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Metadaten
Document Type:Conference Proceeding
Conference Type:Konferenzartikel
Zitierlink: https://opus.hs-offenburg.de/823
Bibliografische Angaben
Title (English):Design and Test of a Gigabit Ethernet MAC for High-Speed HIL-Support
Conference:46. Workshop der Multiprojekt-Chip-Gruppe Baden-Württemberg, Furtwangen, Juli 2011
Author:Alexander Rohleder, Steffen Jäckel, Axel SikoraStaff MemberORCiDGND
Year of Publication:2011
Place of publication:Ulm
Publisher:Hochschule Ulm
First Page:35
Last Page:39
Parent Title (German):Tagungsband zum Workshop der Multiprojekt Chip-Gruppe Baden-Württemberg
Volume:46
ISSN:1682-9221
URL:https://nbn-resolving.org/urn:nbn:de:bsz:ofb1-opus4-60252
Language:English
Inhaltliche Informationen
Institutes:Fakultät Elektrotechnik und Informationstechnik (E+I) (bis 03/2019)
Institutes:Bibliografie
Journals:Tagungsband zum Workshop der Multiprojekt Chip-Gruppe Baden-Württemberg
Formale Angaben
Open Access: Open Access 
 Bronze 
Licence (German):License LogoUrheberrechtlich geschützt