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A Novel Low-Jitter Interface for Synchronization with Low-Cost Integrated IEEE802.11 Chips

  • This paper presents a novel low-jitter interface between a low-cost integrated IEEE802.11 chip and a FPGA. It is designed to be part of system hardware for ultra-precise synchronization between wireless stations. On physical level, it uses Wi-Fi chip coexistence signal lines and UART frame encoding. On its basis, we propose an efficient communication protocol providing precise timestamping ofThis paper presents a novel low-jitter interface between a low-cost integrated IEEE802.11 chip and a FPGA. It is designed to be part of system hardware for ultra-precise synchronization between wireless stations. On physical level, it uses Wi-Fi chip coexistence signal lines and UART frame encoding. On its basis, we propose an efficient communication protocol providing precise timestamping of incoming frames and internal diagnostic mechanisms for detecting communication faults. Meanwhile it is simple enough to be implemented both in low-cost FPGA and commodity IEEE802.11 chip firmware. The results of computer simulation shows that developed FPGA implementation of the proposed protocol can precisely timestamp incoming frames as well as detect most of communication errors even in conditions of high interference. The probability of undetected errors was investigated. The results of this analysis are significant for the development of novel wireless synchronization hardware.show moreshow less

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Metadaten
Document Type:Conference Proceeding
Conference Type:Konferenzartikel
Zitierlink: https://opus.hs-offenburg.de/4548
Bibliografische Angaben
Title (English):A Novel Low-Jitter Interface for Synchronization with Low-Cost Integrated IEEE802.11 Chips
Conference:2020 Systems of Signal Synchronization, Generating and Processing in Telecommunications (SYNCHROINFO), 1-3 July 2020, Svetlogorsk, Russia
Author:Alexey M. Romanov, Maria A. Volkova, Axel SikoraStaff MemberORCiDGND
Year of Publication:2020
Publisher:IEEE
Page Number:6
Parent Title (English):2020 Systems of Signal Synchronization, Generating and Processing in Telecommunications (SYNCHROINFO)
ISBN:978-1-7281-6072-6 (digital)
ISBN:978-1-7281-6073-3 (Print on Demand)
DOI:https://doi.org/10.1109/SYNCHROINFO49631.2020.9166100
Language:English
Inhaltliche Informationen
Institutes:Forschung / ivESK - Institut für verlässliche Embedded Systems und Kommunikationselektronik
Fakultät Elektrotechnik, Medizintechnik und Informatik (EMI) (ab 04/2019)
Institutes:Bibliografie
Formale Angaben
Open Access: Closed Access 
Licence (German):License LogoUrheberrechtlich geschützt