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Development of Fully Printed Oxide Field-Effect Transistors using Graphene Passive Structures
(2019)
During the past decade to the present time, the topic of printed electronics has gained a lot of attention for their potential use in a number of practical applications, including biosensors, photovoltaic devices, RFIDs, flexible displays, large-area circuits, and so on. To fully realize printed electronic components and devices, effective techniques for the printing of passive structures and electrically and chemically compatible materials in the printed devices need to be developed first. The opportunity of using electrically conducting graphene inks will enable the integration of passive structures into active devices, as for example, printed electrolyte-gated transistors (EGTs). Accordingly, in this study, we present the parametric results obtained on fully printed electrolyte-gated transistors having graphene as the passive electrodes, an inorganic oxide semiconductor as the active channel, and a composite solid polymer electrolyte (CSPE) as the gate insulating material. This configuration offers high chemical and electrical stability while at the same time allowing EGT operation at low potentials, implying the distinct advantage of operation at low input voltages. The printed in-plane EGTs we developed exhibit excellent performance with device mobility up to 16 cm2 V–1 s–1, an ION/IOFF ratio of 105, and a subthreshold slope of 120 mV dec–1.
Printed electronics (PE) circuits have several advantages over silicon counterparts for the applications where mechanical flexibility, extremely low-cost, large area, and custom fabrication are required. The custom (personalized) fabrication is a key feature of this technology, enabling customization per application, even in small quantities due to low-cost printing compared with lithography. However, the personalized and on-demand fabrication, the non-standard circuit design, and the limited number of printing layers with larger geometries compared with traditional silicon chip manufacturing open doors for new and unique reverse engineering (RE) schemes for this technology. In this paper, we present a robust RE methodology based on supervised machine learning, starting from image acquisition all the way to netlist extraction. The results show that the proposed RE methodology can reverse engineer the PE circuits with very limited manual effort and is robust against non-standard circuit design, customized layouts, and high variations resulting from the inherent properties of PE manufacturing processes.
Printed electrolyte-gated oxide electronics is an emerging electronic technology in the low voltage regime (≤1 V). Whereas in the past mainly dielectrics have been used for gating the transistors, many recent approaches employ the advantages of solution processable, solid polymer electrolytes, or ion gels that provide high gate capacitances produced by a Helmholtz double layer, allowing for low-voltage operation. Herein, with special focus on work performed at KIT recent advances in building electronic circuits based on indium oxide, n-type electrolyte-gated field-effect transistors (EGFETs) are reviewed. When integrated into ring oscillator circuits a digital performance ranging from 250 Hz at 1 V up to 1 kHz is achieved. Sequential circuits such as memory cells are also demonstrated. More complex circuits are feasible but remain challenging also because of the high variability of the printed devices. However, the device inherent variability can be even exploited in security circuits such as physically unclonable functions (PUFs), which output a reliable and unique, device specific, digital response signal. As an overall advantage of the technology all the presented circuits can operate at very low supply voltages (0.6 V), which is crucial for low-power printed electronics applications.
Electrolyte-gated, printed field-effect transistors exhibit high charge carrier densities in the channel and thus high on-currents at low operating voltages, allowing for the low-power operation of such devices. This behavior is due to the high area-specific capacitance of the device, in which the electrolyte takes the role of the dielectric layer of classical architectures. In this paper, we investigate intrinsic double-layer capacitances of ink-jet printed electrolyte-gated inorganic field-effect transistors in both in-plane and top-gate architectures by means of voltage-dependent impedance spectroscopy. By comparison with deembedding structures, we separate the intrinsic properties of the double-layer capacitance at the transistor channel from parasitic effects and deduce accurate estimates for the double-layer capacitance based on an equivalent circuit fitting. Based on these results, we have performed simulations of the electrolyte cutoff frequency as a function of electrolyte and gate resistances, showing that the top-gate architecture has the potential to reach the kilohertz regime with proper optimization of materials and printing process. Our findings additionally enable accurate modeling of the frequency-dependent capacitance of electrolyte/ion gel-gated devices as required in the small-signal analysis in the circuit simulation.
In the domain of printed electronics (PE), field-effect transistors (FETs) with an oxide semiconductor channel are very promising. In particular, the use of high gate-capacitance of the composite solid polymer electrolytes (CSPEs) as a gate-insulator ensures extremely low voltage requirements. Besides high gate capacitance, such CSPEs are proven to be easily printable, stable in air over wide temperature ranges, and possess high ion conductivity. These CSPEs can be sensitive to moisture, especially for high surface-to-volume ratio printed thin films. In this paper, we provide a comprehensive experimental study on the effect of humidity on CSPE-gated single transistors. At the circuit level, the performance of ring oscillators (ROs) has been compared for various humidity conditions. The experimental results of the electrolyte-gated FETs (EGFETs) demonstrate rather comparable currents between 30%-90% humidity levels. However, the shifted transistor parameters lead to a significant performance change of the RO frequency behavior. The study in this paper shows the need of an impermeable encapsulation for the CSPE-gated FETs to ensure identical performance at all humidity conditions.
Printed electronics can benefit from the deployment of electrolytesas gate insulators,which enables a high gate capacitance per unit area (1–10 μFcm−2) due to the formation of electrical double layers (EDLs). Consequently, electrolyte-gated field-effect transistors (EGFETs) attain high-charge carrier densities already in the subvoltage regime, allowing for low-voltage operation of circuits and systems. This article presents a systematic study of lumped terminal capacitances of printed electrolyte-gated transistors under various dc bias conditions. We perform voltage-dependent impedancemeasurements and separate extrinsic components from the lumped terminal capacitance.
The proposed Meyer-like capacitance model, which also accounts for the nonquasi-static (NQS) effect, agrees well with experimental data. Finally, to verify the model, we implement it in Verilog-A and simulate the transient response of an inverter and a ring oscillator circuit. Simulation results are in good agreement with the measurement data of fabricated devices.
Thermisch angetriebene (Adsorptions-)Kältemaschinen können mit einem verhältnismäßig geringen elektrischen Energieaufwand bzw. mit einer hohen elektrischen Leistungszahl Kälte bereitstel-len. Wird die zum Antrieb erforderliche Wärme aus industrieller Abwärme bereitgestellt, ist diese Kältebereitstellung energetisch effizienter als die Kältebereitstellung über eine Kompressionskäl-temaschine. Wird die Wärme jedoch in Kraft-Wärme-Kopplung bereitgestellt, ist die primärenergetische Bewertung sowohl von mehreren Teilwirkungsgraden als auch den Primärenergiefaktoren für den eingesetzten Brennstoff und die erzeugte bzw. bezogene elektrische Energie abhängig. Eine umfangreiche Messkampagne im Sommer 2018 liefert unter realitätsnahen Randbedingungen in einer Labor umgebung detaillierte Energiekennzahlen für einen typischen Tagesgang des Kältebedarfs. Damit gelingt es, Teilenergiekennwerte für die Planungspraxis abzuleiten und das Gesamtsystem energetisch mit einer konventionellen Kompressionskältemaschine zu vergleichen.
In this article we outline the model development planned within the joint projectModel-based city planningand application in climate change (MOSAIK). The MOSAIK project is funded by the German FederalMinistry of Education and Research (BMBF) within the frameworkUrban Climate Under Change ([UC]2)since 2016. The aim of MOSAIK is to develop a highly-efficient, modern, and high-resolution urban climatemodel that allows to be applied for building-resolving simulations of large cities such as Berlin (Germany).The new urban climate model will be based on the well-established large-eddy simulation code PALM, whichalready has numerous features related to this goal, such as an option for prescribing Cartesian obstacles. Inthis article we will outline those components that will be added or modified in the framework of MOSAIK.Moreover, we will discuss the everlasting issue of acquisition of suitable geographical information as inputdata and the underlying requirements from the model's perspective.
In numerical calculations, guided acoustic waves, localized in two spatial dimensions, have been shown to exist and their properties have been investigated in three different geometries, (i) a half-space consisting of two elastic media with a planar interface inclined to the common surface, (ii) a wedge made of two elastic media with a planar interface, and (iii) the free edge of an elastic layer between two quarter-spaces or two wedge-shaped pieces of a material with elastic properties and density differing from those of the intermediate layer.
For the special case of Poisson media forming systems (i) and (ii), the existence ranges of these 1D guided waves in parameter space have been determined and found to strongly depend on the inclination angle between surface and interface in case (i) and the wedge angle in case (ii). In a system of type (ii) made of two materials with strong acoustic mismatch and in systems of type (iii), leaky waves have been found with a high degree of spatial localization of the associated displacements, although the two materials constituting these structures are isotropic.
Both the fully guided and the leaky waves analyzed in this work could find applications in non-destructive evaluation of composite structures and should be accounted for in geophysical prospecting, for example.
A critical comparison is presented of the two computational approaches employed, namely a semi-analytical finite element scheme and a method based on an expansion of the displacement field in a double series of special functions.
A physical unclonable function (PUF) is a hardware circuit that produces a random sequence based on its manufacturing-induced intrinsic characteristics. In the past decade, silicon-based PUFs have been extensively studied as a security primitive for identification and authentication. The emerging field of printed electronics (PE) enables novel application fields in the scope of the Internet of Things (IoT) and smart sensors. In this paper, we design and evaluate a printed differential circuit PUF (DiffC-PUF). The simulation data are verified by Monte Carlo analysis. Our design is highly scalable while consisting of a low number of printed transistors. Furthermore, we investigate the best operating point by varying the PUF challenge configuration and analyzing the PUF security metrics in order to achieve high robustness. At the best operating point, the results show areliability of 98.37% and a uniqueness of 50.02%, respectively. This analysis also provides useful and comprehensive insights into the design of hybrid or fully printed PUF circuits. In addition, the proposed printed DiffC-PUF core has been fabricated with electrolyte-gated field-effect transistor technology to verify our design in hardware.