Refine
Year of publication
- 2020 (87) (remove)
Document Type
- Conference Proceeding (33)
- Article (reviewed) (23)
- Article (unreviewed) (9)
- Letter to Editor (6)
- Patent (5)
- Contribution to a Periodical (3)
- Report (3)
- Book (1)
- Part of a Book (1)
- Doctoral Thesis (1)
- Moving Images (1)
- Other (1)
Conference Type
- Konferenzartikel (30)
- Konferenz-Abstract (1)
- Konferenz-Poster (1)
- Sonstiges (1)
Language
- English (64)
- German (22)
- Other language (1)
Has Fulltext
- no (87) (remove)
Is part of the Bibliography
- yes (87)
Keywords
- Ablation (2)
- Cardiac Resynchronization Therapy (2)
- Götz von Berlichingen (2)
- Herzrhythmusmodell (2)
- Johann Sebastian Bach (2)
- Neurostimulation (2)
- Prothetik (2)
- Regelungstechnik (2)
- RoboCup (2)
- Röntgen (2)
Institute
- Fakultät Elektrotechnik, Medizintechnik und Informatik (EMI) (ab 04/2019) (87) (remove)
Open Access
- Closed Access (45)
- Open Access (34)
- Bronze (4)
- Closed (1)
The number of use cases for autonomous vehicles is increasing day by day especially in commercial applications. One important application of autonomous vehicles can be found within the parcel delivery section. Here, autonomous cars can massively help to reduce delivery efforts and time by supporting the courier actively. One important component of course is the autonomous vehicle itself. Nevertheless, beside the autonomous vehicle, a flexible and secure communication architecture also is a crucial key component impacting the overall performance of such system since it is required to allow continuous interactions between the vehicle and the other components of the system. The communication system must provide a reliable and secure architecture that is still flexible enough to remain practical and to address several use cases. In this paper, a robust communication architecture for such autonomous fleet-based systems is proposed. The architecture provides a reliable communication between different system entities while keeping those communications secure. The architecture uses different technologies such as Bluetooth Low Energy (BLE), cellular networks and Low Power Wide Area Network (LPWAN) to achieve its goals.
Modeling of Random Variations in a Switched Capacitor Circuit based Physically Unclonable Function
(2020)
The Internet of Things (IoT) is expanding to a wide range of fields such as home automation, agriculture, environmental monitoring, industrial applications, and many more. Securing tens of billions of interconnected devices in the near future will be one of the biggest challenges. IoT devices are often constrained in terms of computational performance, area, and power, which demand lightweight security solutions. In this context, hardware-intrinsic security, particularly physically unclonable functions (PUFs), can provide lightweight identification and authentication for such devices. In this paper, random capacitor variations in a switched capacitor PUF circuit are used as a source of entropy to generate unique security keys. Furthermore, a mathematical model based on the ordinary least square method is developed to describe the relationship between random variations in capacitors and the resulting output voltages. The model is used to filter out systematic variations in circuit components to improve the quality of the extracted secrets.
Bei bimodaler Cochlea-Implantat-/Hörgerät-Versorgung kann es aufgrund seitenverschiedener Signalverarbeitung zu einer zeitlich versetzten Stimulation der beiden Modalitäten kommen. Jüngste Studien haben gezeigt, dass durch zeitlichen Abgleich der Modalitäten die Schalllokalisation bei bimodaler Versorgung verbessert werden kann. Um solch einen Abgleich vornehmen zu können, ist die messtechnische Bestimmung der Durchlaufzeit von Hörgeräten erforderlich. Kommerziell verfügbare Hörgerätemessboxen können diese Werte häufig liefern. Die dazu verwendete Signalverarbeitung wird dabei aber oft nicht vollständig offengelegt. In dieser Arbeit wird ein alternativer und nachvollziehbarer Ansatz zum Design eines simplen Messaufbaus basierend auf einem Arduino DUE Mikrocontroller-Board vorgestellt. Hierzu wurde ein Messtisch im 3D-Druck gefertigt, auf welchem Hörgeräte über einen 2-ccm-Kuppler an ein Messmikrofon angeschlossen werden können. Über einen Latenzvergleich mit dem simultan erfassten Signal eines Referenzmikrofons kann die Durchlaufzeit von Hörgeräten bestimmt werden. Frequenzspezifische Durchlaufzeiten werden mittels einer Kreuzkorrelation zwischen Ziel- und Referenzsignal errechnet. Aufnahme, Ausgabe und Speicherung der Signale erfolgt über einen ATMEL SAM3X8E Mikrocontroller, welcher auf dem Arduino DUE-Board verbaut ist. Über eigens entworfene elektronische Schaltungen werden die Mikrofone und der verwendete Lautsprecher angesteuert. Nach Abschluss einer Messung (Messdauer ca. 5 s) werden die Messdaten seriell an einen PC übertragen, auf dem die Datenauswertung mittels MATLAB erfolgt. Erste Validierungen zeigten eine hohe Stabilität der Messergebnisse mit sehr geringen Standardabweichungen im Bereich weniger Mikrosekunden für Pegel zwischen 50 und 75 dB (A). Der Messaufbau wird in laufenden Studien zur Quantifizierung der Durchlaufzeit von Hörgeräten verwendet.
Many different methods, such as screen printing, gravure, flexography, inkjet etc., have been employed to print electronic devices. Depending on the type and performance of the devices, processing is done at low or high temperature using precursor- or particle-based inks. As a result of the processing details, devices can be fabricated on flexible or non-flexible substrates, depending on their temperature stability. Furthermore, in order to reduce the operating voltage, printed devices rely on high-capacitance electrolytes rather than on dielectrics. The printing resolution and speed are two of the major challenging parameters for printed electronics. High-resolution printing produces small-size printed devices and high-integration densities with minimum materials consumption. However, most printing methods have resolutions between 20 and 50 μm. Printing resolutions close to 1 μm have also been achieved with optimized process conditions and better printing technology.
The final physical dimensions of the devices pose severe limitations on their performance. For example, the channel lengths being of this dimension affect the operating frequency of the thin-film transistors (TFTs), which is inversely proportional to the square of channel length. Consequently, short channels are favorable not only for high-frequency applications but also for high-density integration. The need to reduce this dimension to substantially smaller sizes than those possible with today’s printers can be fulfilled either by developing alternative printing or stamping techniques, or alternative transistor geometries. The development of a polymer pen lithography technique allows scaling up parallel printing of a large number of devices in one step, including the successive printing of different materials. The introduction of an alternative transistor geometry, namely the vertical Field Effect Transistor (vFET), is based on the idea to use the film thickness as the channel length, instead of the lateral dimensions of the printed structure, thus reducing the channel length by orders of magnitude. The improvements in printing technologies and the possibilities offered by nanotechnological approaches can result in unprecedented opportunities for the Internet of Things (IoT) and many other applications. The vision of printing functional materials, and not only colors as in conventional paper printing, is attractive to many researchers and industries because of the added opportunities when using flexible substrates such as polymers and textiles. Additionally, the reduction of costs opens new markets. The range of processing techniques covers laterally-structured and large-area printing technologies, thermal, laser and UV-annealing, as well as bonding techniques, etc. Materials, such as conducting, semiconducting, dielectric and sensing materials, rigid and flexible substrates, protective coating, organic, inorganic and polymeric substances, energy conversion and energy storage materials constitute an enormous challenge in their integration into complex devices.
Die Erfindung betrifft eine Schaltungsanordnung (10) für ein Kraftfahrzeug, mit einer Hochvolt-Batterie (12) zum Speichern von elektrischer Energie, mit wenigstens einer elektrischen Maschine (14) zum Antreiben des Kraftfahrzeugs, mit einem Stromrichter (16), mittels welchem von der Hochvolt-Batterie (12) bereitstellbare Hochvolt-Gleichspannung in Hochvolt-Wechselspannung zum Betreiben der elektrischen Maschine (14) umwandelbar ist, und mit einem Ladeanschluss (20) zum Bereitstellen von elektrischer Energie zum Laden der Hochvolt-Batterie (12), wobei der Stromrichter (16) als ein Drei-Stufen-Stromrichter ausgebildet ist und wenigstens eine einer Phase (u) der elektrischen Maschine (14) zugeordnete Schaltereinheit (46) aufweist, welche zwei in Reihe geschaltete Schaltergruppen (52, 54) umfasst, die jeweils zwei in Reihe geschaltete IGBTs (T11, T12, T13, T14) aufweisen, wobei zwischen den IGBTs (T11, T12) einer der Schaltergruppen (52, 54) ein Anschluss (64) angeordnet ist, welcher direkt mit einer Leitung (34) des Ladeanschlusses (20) elektrisch verbunden ist.
Electrolyte-gated thin-film transistors (EGTs) with indium oxide channel, and expected lifetime of three months, enable low-voltage operation (~1 V) in the field of printed electronics (PEs). The channel width of our printed EGTs is varied between 200 and 1000 μm, whereas a channel length between 10 and 100 μm is used. Due to the lack of uniform performance p-type metal oxide semiconductors, n-type EGTs and passive elements are used to design circuits. For logic gates, transistor-resistor logic has been employed so far, but depletion and enhancement-mode EGTs in a transistor-transistor logic boost the circuit performance in terms of delay and signal swing. In this article, the threshold voltage of the EGT, which determines the operation mode, is tuned through sizing of the EGTs channel geometry. The feasibility of both transistor operation modes is demonstrated for logic gates and ring oscillators. An inverter operating at a supply voltage of 1 V shows a maximum gain of 9.6 and a propagation delay time of 0.7 ms, which represents an improvement of ~ 2x for the gain and oscillation frequency, in comparison with the resistor-transistor logic design. Moreover, the power consumption is reduced by 6x.
Oxide semiconductors have the potential to increase the performance of inkjet printed microelectronic devices such as field-effect transistors (FETs), due to their high electron mobilities. Typical metal oxides are n-type semiconductors, while p-type oxides, although realizable, exhibit lower carriermobilities. Therefore, the circuit design based on oxide semiconductors is mostly in n-type logic only. Here we present an inkjet printed pn-diode based on p- and n-type oxide semiconductors.Copper oxide or nickel oxide is used as p-typesemiconductor whereas n-typesemiconductor is realized with indium oxide. Themeasurements show that the pn-diodes operate in the voltage window typical for printed electronics and the emission coefficient is 1.505 and 2.199 for the copper oxide based and nickel oxidebased pn-diode, respectively.Furthermore, a pn-diode model is developed and integrable into a circuit simulator.
In this work a method for the estimation of current slopes induced by inverters operating interior permanent magnet synchronous machines is presented. After the derivation of the estimation algorithm, the requirements for a suitable sensor setup in terms of accuracy, dynamic and electromagnetic interference are discussed. The boundary conditions for the estimation algorithm are presented with respect to application within high power traction systems. The estimation algorithm is implemented on a field programmable gateway array. This moving least-square algorithm offers the advantage that it is not dependent on vectors and therefore not every measured value has to be stored. The summation of all measured values leads to a significant reduction of the required storage units and thus decreases the hardware requirements. The algorithm is designed to be calculated within the dead time of the inverter. Appropriate countermeasures for disturbances and hardware restrictions are implemented. The results are discussed afterwards.