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Durch den digitalen Wandel, sowie durch die an Benutzerfreundlichkeit und Leistung zunehmenden technischen Geräte im Endbenutzer-Bereich beginnt die Bedeutung von Augmented-Reality Applikationen zu wachsen. Daher ist das Ziel dieser Arbeit die Entwicklung einer Engine auf iOS Basis, zur Dastellung von Augmented-Reality Inhalten. Die Engine wurde nach dem Vorbild von Komponenten-basierten Game Engines entworfen, da diese beinahe identische Anforderungen besitzen. Die, im Rahmen dieser Arbeit erstellte Engine wurde mit Unterstützung der 5d lab Gmb entwickelt. Durch die Verwendung des, nach Erfahrungswerten, schnellsten Mobile Augmented Reality SDK und einer gelungenen Engine-Architektur konnte ein Produkt entwickelt werden, dass mit bestehenden Applikationen konkurrenzfähig ist.
Im ASIC Design Center der Hochschule Offenburg wird ein Design Kit für die UMC 0.18μm Faraday Technologie aufbereitet. Dabei werden alle benötigten Dateien, welche für einen zunächst rein digitalen Chipentwurf unter Verwendung der Synopsys, Cadence und Mentor Tools benötigt werden, für den UMC 0.18μm Prozess zusammengestellt.
The objective of this thesis is the conceptual design of a battery management system for the first prototype of the UWC (University of the Western Cape) Modular Battery System. The battery system is a lithium-ion battery that aims to be used in renewable energy systems and for niche electric vehicles such as golf carts.
The concept that is introduced in this thesis comprises the parameter monitoring, the safety management and has its main focus on an accurate state of charge estimation.
Another battery system that was already implemented is used as base for the parameter monitoring and the safety management for the new battery management system. In contrast to that, the concept for the state of charge estimation must be developed completely.
Different methods for the state of charge estimation which are based on the measured voltage, current and temperature are discussed, evaluated and the chosen method is conceived in this thesis. The method used for the state of charge estimation is different for the time when the battery is active than when it is inactive. During charge and discharge Coulomb counting is used and when the cell is inactive voltage versus state of charge lookup tables are used to update the estimation.
To have an accurate estimation when the cell is inactive only for a short time, a model of the voltage relaxation is used to predict the voltage when the cells are in equilibrium. This allows the algorithm to reset the state of charge that is estimated by Coulomb counting – which tends to have a growing error over time – frequently.
To evaluate the accuracy of the voltage prediction, cell tests were executed where the voltage relaxation was sampled. The recursive least square method to predict the end voltage was tested with a MATLAB programme. With the help of voltage versus state of charge lookup tables it was possible to determine the state of charge accuracy with the accuracy of the voltage prediction.
An der FH Offenburg arbeiten seit Ende 1989 in einem Team die Professoren Dr. Jansen, Dr. Schüssele, die wissenschaftlichen Mitarbeiter Bernd Reinke, Martin Jörger und die Diplomanden Hans Fiesel, Otmar Feißt an dem Entwurf eines Nachrichtenempfängers. Im Rahmen dieses Projekts, genannt GPS-Projekt (GPS = Global Positioning System), wurde im Herbst 1990 ein experimenteller Empfänger in Betrieb genommen. Nachdem die Testergebnisse gezeigt hatten,daß das Konzept der Anlage stimmte, ging es nun um die Miniaturisieriung, Integration und Optimierung der Schaltung. Außerdem sollte der bisher verwendete PC durch einen auf der Platine befindlichen Mikroprozessor ersetzt werden. Im Zusammenhang mit dem GPS-Projekt wurden bisher im Offenburger ASIC-Labor eine Analogschaltung auf einem B500, drei LCA Designs und diverse GAL's entwickelt.
Zur Zeit arbeiten mehrere Diplomanden an der zweiten Generation des Empfängers. Meine Aufgabe besteht darin, die dort noch in drei LCA's untergebrachte digitale Logik sowie einen Teil des bisherigen PC-Interface in einem IMS Gate Forrest zu integrieren. Außerdem muß die Logik von 8 Bit auf einen 16 Bit breiten Datenbus umgestellt und an die neue Peripherie des Mikroprozessors angepasst werden. Damit soll die jetzige Digital-Platine noch weiter verkleinert werden. Wesentlich ist dabei die Umsetzung der zahlreichen Zähler- und Registerstrukturen in einem Gate Forrest. Als Arbeitsmittel stehen Apollo Workstations mit Mentor Software zur Verfügung.
In this paper an RFID/NFC (ISO 15693 standard) based inductively powered passive SoC (system on chip) for biomedical applications is presented. A brief overview of the system design, layout techniques and verification method is dis-cussed here. The SoC includes an integrated 32 bit microcontroller, sensor interface circuit, analog to digital converter, integrated RAM, ROM and some other peripherals required for the complete passive operation. The entire chip is realized in CMOS 0.18 μm technology with a chip area of 1.52mm x 3.24 mm.
An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications
(2018)
Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μm CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 mm2. The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μW. The analog part of the design consumes only 36 μW, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches.