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Formal verification (FV) is considered by many to be complicated and to require considerable mathematical knowledge for successful application. We have developed a methodology in which we have added formal verification to the verification process without requiring any knowledge of formal verification languages. We use only finite-state machine notation, which is familiar and intuitive to designers. Another problem associated with formal verification is state-space explosion. If that occurs, no result is returned; our method switches to random simulation after one hour without results, and no effort is lost. We have compared FV against random simulation with respect to development time, and our results indicate that FV is at least as fast as random simulation. FV is superior in terms of verification quality, however, because it is exhaustive.
In addition to traditional methods in product development, the increasing availability of additive manufacturing AM technologies offer new opportunities in product development processes today. This contribution explores several ways in which AM can productively be used in education. New to this approach is amongst others that the students assemble and install the 3D-printers themselves. In two case studies is demonstrated how students in design education are able to autonomously research and realize technical possibilities and limitations of AM technologies, as well as economic constraints.