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Physical unclonable functions (PUFs) are increasingly generating attention in the field of hardware-based security for the Internet of Things (IoT). A PUF, as its name implies, is a physical element with a special and unique inherent characteristic and can act as the security anchor for authentication and cryptographic applications. Keeping in mind that the PUF outputs are prone to change in the presence of noise and environmental variations, it is critical to derive reliable keys from the PUF and to use the maximum entropy at the same time. In this work, the PUF output positioning (POP) method is proposed, which is a novel method for grouping the PUF outputs in order to maximize the extracted entropy. To achieve this, an offset data is introduced as helper data, which is used to relax the constraints considered for the grouping of PUF outputs, and deriving more entropy, while reducing the secret key error bits. To implement the method, the key enrollment and key generation algorithms are presented. Based on a theoretical analysis of the achieved entropy, it is proven that POP can maximize the achieved entropy, while respecting the constraints induced to guarantee the reliability of the secret key. Moreover, a detailed security analysis is presented, which shows the resilience of the method against cyber-security attacks. The findings of this work are evaluated by applying the method on a hybrid printed PUF, where it can be practically shown that the proposed method outperforms other existing group-based PUF key generation methods.
Bei bimodaler Cochlea-Implantat-/Hörgerät-Versorgung kann es aufgrund seitenverschiedener Signalverarbeitung zu einer zeitlich versetzten Stimulation der beiden Modalitäten kommen. Jüngste Studien haben gezeigt, dass durch zeitlichen Abgleich der Modalitäten die Schalllokalisation bei bimodaler Versorgung verbessert werden kann. Um solch einen Abgleich vornehmen zu können, ist die messtechnische Bestimmung der Durchlaufzeit von Hörgeräten erforderlich. Kommerziell verfügbare Hörgerätemessboxen können diese Werte häufig liefern. Die dazu verwendete Signalverarbeitung wird dabei aber oft nicht vollständig offengelegt. In dieser Arbeit wird ein alternativer und nachvollziehbarer Ansatz zum Design eines simplen Messaufbaus basierend auf einem Arduino DUE Mikrocontroller-Board vorgestellt. Hierzu wurde ein Messtisch im 3D-Druck gefertigt, auf welchem Hörgeräte über einen 2-ccm-Kuppler an ein Messmikrofon angeschlossen werden können. Über einen Latenzvergleich mit dem simultan erfassten Signal eines Referenzmikrofons kann die Durchlaufzeit von Hörgeräten bestimmt werden. Frequenzspezifische Durchlaufzeiten werden mittels einer Kreuzkorrelation zwischen Ziel- und Referenzsignal errechnet. Aufnahme, Ausgabe und Speicherung der Signale erfolgt über einen ATMEL SAM3X8E Mikrocontroller, welcher auf dem Arduino DUE-Board verbaut ist. Über eigens entworfene elektronische Schaltungen werden die Mikrofone und der verwendete Lautsprecher angesteuert. Nach Abschluss einer Messung (Messdauer ca. 5 s) werden die Messdaten seriell an einen PC übertragen, auf dem die Datenauswertung mittels MATLAB erfolgt. Erste Validierungen zeigten eine hohe Stabilität der Messergebnisse mit sehr geringen Standardabweichungen im Bereich weniger Mikrosekunden für Pegel zwischen 50 und 75 dB (A). Der Messaufbau wird in laufenden Studien zur Quantifizierung der Durchlaufzeit von Hörgeräten verwendet.
The increasing use of artificial intelligence (AI) technologies across application domains has prompted our society to pay closer attention to AI’s trustworthiness, fairness, interpretability, and accountability. In order to foster trust in AI, it is important to consider the potential of interactive visualization, and how such visualizations help build trust in AI systems. This manifesto discusses the relevance of interactive visualizations and makes the following four claims: i) trust is not a technical problem, ii) trust is dynamic, iii) visualization cannot address all aspects of trust, and iv) visualization is crucial for human agency in AI.
Electrolyte-gated thin-film transistors (EGTs) with indium oxide channel, and expected lifetime of three months, enable low-voltage operation (~1 V) in the field of printed electronics (PEs). The channel width of our printed EGTs is varied between 200 and 1000 μm, whereas a channel length between 10 and 100 μm is used. Due to the lack of uniform performance p-type metal oxide semiconductors, n-type EGTs and passive elements are used to design circuits. For logic gates, transistor-resistor logic has been employed so far, but depletion and enhancement-mode EGTs in a transistor-transistor logic boost the circuit performance in terms of delay and signal swing. In this article, the threshold voltage of the EGT, which determines the operation mode, is tuned through sizing of the EGTs channel geometry. The feasibility of both transistor operation modes is demonstrated for logic gates and ring oscillators. An inverter operating at a supply voltage of 1 V shows a maximum gain of 9.6 and a propagation delay time of 0.7 ms, which represents an improvement of ~ 2x for the gain and oscillation frequency, in comparison with the resistor-transistor logic design. Moreover, the power consumption is reduced by 6x.
Oxide semiconductors have the potential to increase the performance of inkjet printed microelectronic devices such as field-effect transistors (FETs), due to their high electron mobilities. Typical metal oxides are n-type semiconductors, while p-type oxides, although realizable, exhibit lower carriermobilities. Therefore, the circuit design based on oxide semiconductors is mostly in n-type logic only. Here we present an inkjet printed pn-diode based on p- and n-type oxide semiconductors.Copper oxide or nickel oxide is used as p-typesemiconductor whereas n-typesemiconductor is realized with indium oxide. Themeasurements show that the pn-diodes operate in the voltage window typical for printed electronics and the emission coefficient is 1.505 and 2.199 for the copper oxide based and nickel oxidebased pn-diode, respectively.Furthermore, a pn-diode model is developed and integrable into a circuit simulator.
In the domain of printed electronics (PE), field-effect transistors (FETs) with an oxide semiconductor channel are very promising. In particular, the use of high gate-capacitance of the composite solid polymer electrolytes (CSPEs) as a gate-insulator ensures extremely low voltage requirements. Besides high gate capacitance, such CSPEs are proven to be easily printable, stable in air over wide temperature ranges, and possess high ion conductivity. These CSPEs can be sensitive to moisture, especially for high surface-to-volume ratio printed thin films. In this paper, we provide a comprehensive experimental study on the effect of humidity on CSPE-gated single transistors. At the circuit level, the performance of ring oscillators (ROs) has been compared for various humidity conditions. The experimental results of the electrolyte-gated FETs (EGFETs) demonstrate rather comparable currents between 30%-90% humidity levels. However, the shifted transistor parameters lead to a significant performance change of the RO frequency behavior. The study in this paper shows the need of an impermeable encapsulation for the CSPE-gated FETs to ensure identical performance at all humidity conditions.
Printed electrolyte-gated oxide electronics is an emerging electronic technology in the low voltage regime (≤1 V). Whereas in the past mainly dielectrics have been used for gating the transistors, many recent approaches employ the advantages of solution processable, solid polymer electrolytes, or ion gels that provide high gate capacitances produced by a Helmholtz double layer, allowing for low-voltage operation. Herein, with special focus on work performed at KIT recent advances in building electronic circuits based on indium oxide, n-type electrolyte-gated field-effect transistors (EGFETs) are reviewed. When integrated into ring oscillator circuits a digital performance ranging from 250 Hz at 1 V up to 1 kHz is achieved. Sequential circuits such as memory cells are also demonstrated. More complex circuits are feasible but remain challenging also because of the high variability of the printed devices. However, the device inherent variability can be even exploited in security circuits such as physically unclonable functions (PUFs), which output a reliable and unique, device specific, digital response signal. As an overall advantage of the technology all the presented circuits can operate at very low supply voltages (0.6 V), which is crucial for low-power printed electronics applications.
Interpreting seismic data requires the characterization of a number of key elements such as the position of faults and main reflections, presence of structural bodies, and clustering of areas exhibiting a similar amplitude versus angle response. Manual interpretation of geophysical data is often a difficult and time-consuming task, complicated by lack of resolution and presence of noise. In recent years, approaches based on convolutional neural networks have shown remarkable results in automating certain interpretative tasks. However, these state-of-the-art systems usually need to be trained in a supervised manner, and they suffer from a generalization problem. Hence, it is highly challenging to train a model that can yield accurate results on new real data obtained with different acquisition, processing, and geology than the data used for training. In this work, we introduce a novel method that combines generative neural networks with a segmentation task in order to decrease the gap between annotated training data and uninterpreted target data. We validate our approach on two applications: the detection of diffraction events and the picking of faults. We show that when transitioning from synthetic training data to real validation data, our workflow yields superior results compared to its counterpart without the generative network.
Printed electronics (PE) circuits have several advantages over silicon counterparts for the applications where mechanical flexibility, extremely low-cost, large area, and custom fabrication are required. The custom (personalized) fabrication is a key feature of this technology, enabling customization per application, even in small quantities due to low-cost printing compared with lithography. However, the personalized and on-demand fabrication, the non-standard circuit design, and the limited number of printing layers with larger geometries compared with traditional silicon chip manufacturing open doors for new and unique reverse engineering (RE) schemes for this technology. In this paper, we present a robust RE methodology based on supervised machine learning, starting from image acquisition all the way to netlist extraction. The results show that the proposed RE methodology can reverse engineer the PE circuits with very limited manual effort and is robust against non-standard circuit design, customized layouts, and high variations resulting from the inherent properties of PE manufacturing processes.
Printed electronics (PE) is a fast-growing field with promising applications in wearables, smart sensors, and smart cards, since it provides mechanical flexibility, and low-cost, on-demand, and customizable fabrication. To secure the operation of these applications, true random number generators (TRNGs) are required to generate unpredictable bits for cryptographic functions and padding. However, since the additive fabrication process of the PE circuits results in high intrinsic variations due to the random dispersion of the printed inks on the substrate, constructing a printed TRNG is challenging. In this article, we exploit the additive customizable fabrication feature of inkjet printing to design a TRNG based on electrolyte-gated field-effect transistors (EGFETs). We also propose a printed resistor tuning flow for the TRNG circuit to mitigate the overall process variation of the TRNG so that the generated bits are mostly based on the random noise in the circuit, providing a true random behavior. The simulation results show that the overall process variation of the TRNGs is mitigated by 110 times, and the generated bitstream of the tuned TRNGs passes the National Institute of Standards and Technology - Statistical Test Suite. For the proof of concept, the proposed TRNG circuit was fabricated and tuned. The characterization results of the tuned TRNGs prove that the TRNGs generate random bitstreams at the supply voltage of down to 0.5 V. Hence, the proposed TRNG design is suitable to secure low-power applications in this domain.
Printed electronics (PE) enables disruptive applications in wearables, smart sensors, and healthcare since it provides mechanical flexibility, low cost, and on-demand fabrication. The progress in PE raises trust issues in the supply chain and vulnerability to reverse engineering (RE) attacks. Recently, RE attacks on PE circuits have been successfully performed, pointing out the need for countermeasures against RE, such as camouflaging. In this article, we propose a printed camouflaged logic cell that can be inserted into PE circuits to thwart RE. The proposed cell is based on three components achieved by changing the fabrication process that exploits the additive manufacturing feature of PE. These components are optically look-alike, while their electrical behaviors are different, functioning as a transistor, short, and open. The properties of the proposed cell and standard PE cells are compared in terms of voltage swing, delay, power consumption, and area. Moreover, the proposed camouflaged cell is fabricated and characterized to prove its functionality. Furthermore, numerous camouflaged components are fabricated, and their (in)distinguishability is assessed to validate their optical similarities based on the recent RE attacks on PE. The results show that the proposed cell is a promising candidate to be utilized in camouflaging PE circuits with negligible overhead.
Advances in printed electronics (PE) enables new applications, particularly in ultra-low-cost domains. However, achieving high-throughput printing processes and manufacturing yield is one of the major challenges in the large-scale integration of PE technology. In this article, we present a programmable printed circuit based on an efficient printed lookup table (pLUT) to address these challenges by combining the advantages of the high-throughput advanced printing and maskless point-of-use final configuration printing. We propose a novel pLUT design which is more efficient in PE realization compared to existing LUT designs. The proposed pLUT design is simulated, fabricated, and programmed as different logic functions with inkjet printed conductive ink to prove that it can realize digital circuit functionality with the use of programmability features. The measurements show that the fabricated LUT design is operable at 1 V.
Printed electronics can benefit from the deployment of electrolytesas gate insulators,which enables a high gate capacitance per unit area (1–10 μFcm−2) due to the formation of electrical double layers (EDLs). Consequently, electrolyte-gated field-effect transistors (EGFETs) attain high-charge carrier densities already in the subvoltage regime, allowing for low-voltage operation of circuits and systems. This article presents a systematic study of lumped terminal capacitances of printed electrolyte-gated transistors under various dc bias conditions. We perform voltage-dependent impedancemeasurements and separate extrinsic components from the lumped terminal capacitance.
The proposed Meyer-like capacitance model, which also accounts for the nonquasi-static (NQS) effect, agrees well with experimental data. Finally, to verify the model, we implement it in Verilog-A and simulate the transient response of an inverter and a ring oscillator circuit. Simulation results are in good agreement with the measurement data of fabricated devices.
Electrolyte-gated, printed field-effect transistors exhibit high charge carrier densities in the channel and thus high on-currents at low operating voltages, allowing for the low-power operation of such devices. This behavior is due to the high area-specific capacitance of the device, in which the electrolyte takes the role of the dielectric layer of classical architectures. In this paper, we investigate intrinsic double-layer capacitances of ink-jet printed electrolyte-gated inorganic field-effect transistors in both in-plane and top-gate architectures by means of voltage-dependent impedance spectroscopy. By comparison with deembedding structures, we separate the intrinsic properties of the double-layer capacitance at the transistor channel from parasitic effects and deduce accurate estimates for the double-layer capacitance based on an equivalent circuit fitting. Based on these results, we have performed simulations of the electrolyte cutoff frequency as a function of electrolyte and gate resistances, showing that the top-gate architecture has the potential to reach the kilohertz regime with proper optimization of materials and printing process. Our findings additionally enable accurate modeling of the frequency-dependent capacitance of electrolyte/ion gel-gated devices as required in the small-signal analysis in the circuit simulation.
Rectifiersare vital electronic circuits for signal and power conversion in various smart sensor applications. The ability to process low input voltage levels, for example, from vibrational energy harvesters is a major challenge with existing passive rectifiers in printed electronics, stemming mainly from the built-in potential of the diode's p-njunction. To address this problem, in this work, we design, fabricate, and characterize an inkjet-printed full-wave rectifier using diode-connected electrolyte-gated thin-film transistors (EGTs). Using both experimental and simulation approaches, we investigate how the rectifier can benefit from the near-zero threshold voltage of transistors, which can be enabled by proper channel geometry setting in EGT technology. The presented circuit can be operated at 1-V input voltage, featuring a remarkably small voltage loss of 140 mV and a cutoff frequency of ~300 Hz. Below the cutoff frequency, more than 2.6-μW dc power is obtained over the load resistances ranging from 5 to 20 kQ. Furthermore, experiments show that the circuit can work with an input amplitude down to 500 mV. This feature makes the presented design highly suitable for a variety of energy-harvesting applications.
Diese Arbeit beschäftigt sich mit der Biomechanik der Halswirbelsäule (HWS) beim Umgang mit dem Smartphone. Die Kräfte, die auf Wirbelkörper, Wirbelgelenke, Bandscheiben, Muskeln und Bänder wirken, werden mit steigendem Flexionswinkel der HWS größer. Die Beschwerden hingegen, welche der Smartphone-Nacken hervorruft, sind meist akut und mit regelmäßiger Bewegung und der Stärkung der Nackenmuskulatur gut zu behandeln. Eine Therapie ist somit auch zur Vorbeugung geeignet. Doch die Langzeitauswirkungen sind nicht außer Acht zu lassen, denn durch die steigenden Nutzungsmöglichkeiten der Smartphones steigt auch der durchschnittliche tägliche Gebrauch stärker an. So wird vor allem die tägliche Bildschirmzeit bei Jugendlichen immer länger. Das aktuell noch akute Krankheitsbild des Smartphone-Nackens, das nur selten einen chronischen Verlauf nimmt und Langzeitschäden verursacht, könnte sich durch fehlende oder zu späte Maßnahmen zu einem größeren chronischen Krankheitsbild entwickeln.
Many commonly well-performing convolutional neural network models have shown to be susceptible to input data perturbations, indicating a low model robustness. To reveal model weaknesses, adversarial attacks are specifically optimized to generate small, barely perceivable image perturbations that flip the model prediction. Robustness against attacks can be gained by using adversarial examples during training, which in most cases reduces the measurable model attackability. Unfortunately, this technique can lead to robust overfitting, which results in non-robust models. In this paper, we analyze adversarially trained, robust models in the context of a specific network operation, the downsampling layer, and provide evidence that robust models have learned to downsample more accurately and suffer significantly less from downsampling artifacts, aka. aliasing, than baseline models. In the case of robust overfitting, we observe a strong increase in aliasing and propose a novel early stopping approach based on the measurement of aliasing.
Aerosol particles play an important role in the climate system by absorbing and scattering radiation and influencing cloud properties. They are also one of the biggest sources of uncertainty for climate modeling. Many climate models do not include aerosols in sufficient detail due to computational constraints. To represent key processes, aerosol microphysical properties and processes have to be accounted for. This is done in the ECHAM-HAM (European Center for Medium-Range Weather Forecast-Hamburg-Hamburg) global climate aerosol model using the M7 microphysics, but high computational costs make it very expensive to run with finer resolution or for a longer time. We aim to use machine learning to emulate the microphysics model at sufficient accuracy and reduce the computational cost by being fast at inference time. The original M7 model is used to generate data of input–output pairs to train a neural network (NN) on it. We are able to learn the variables’ tendencies achieving an average R² score of 77.1%. We further explore methods to inform and constrain the NN with physical knowledge to reduce mass violation and enforce mass positivity. On a Graphics processing unit (GPU), we achieve a speed-up of up to over 64 times faster when compared to the original model.