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A new RFID/NFC (ISO 15693 standard) based inductively powered passive SoC (System on chip) for biomedical applications is presented here. The proposed SOC consists of an integrated 32 bit microcontroller, RFID/NFC frontend, sensor interface circuit, analog to digital converter and some peripherals such as timer, SPI interface and memory devices. An energy harvesting unit supplies the power required for the entire system for complete passive operation. The complete chip is realized on CMOS 0.18 μm technology with a chip area of 1.5 mm × 3.0 mm.
High mobility, electrolyte-gated transistors (EGTs) show high DC performance at low voltages (< 2 V). To model those EGTs, we have used different models for the below and the above threshold regime with appropriate interpolation to ensure continuity and smoothness over all regimes. This empirical model matches very well with our measured results obtained by the electrical characterization of EGTs.
Electrolyte-Gated Field-Effect Transistors Based on Oxide Semiconductors: Fabrication and Modeling
(2017)
An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications
(2018)
Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μm CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 mm2. The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μW. The analog part of the design consumes only 36 μW, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches.
Oxide semiconductors are highly promising candidates for the most awaited, next-generation electronics, namely, printed electronics. As a fabrication route for the solution-processed/printed oxide semiconductors, photonic curing is becoming increasingly popular, as compared to the conventional thermal curing method; the former offers numerous advantages over the latter, such as low process temperatures and short exposure time and thereby, high throughput compatibility. Here, using dissimilar photonic curing concepts (UV–visible light and UV-laser), we demonstrate facile fabrication of high performance In2O3 field-effect transistors (FETs). Beside the processing related issues (temperature, time etc.), the other known limitation of oxide electronics is the lack of high performance p-type semiconductors, which can be bypassed using unipolar logics from high mobility n-type semiconductors alone. Interestingly, here we have found that our chosen distinct photonic curing methods can offer a large variation in threshold voltage, when they are fabricated from the same precursor ink. Consequently, both depletion and enhancement-mode devices have been achieved which can be used as the pull-up and pull-down transistors in unipolar inverters. The present device fabrication recipe demonstrates fast processing of low operation voltage, high performance FETs with large threshold voltage tunability.
A printed electronics technology has the advantage of additive and extremely low-cost fabrication compared with the conventional silicon technology. Specifically, printed electrolyte-gated field-effect transistors (EGFETs) are attractive for low-cost applications in the Internet-of-Things domain as they can operate at low supply voltages. In this paper, we propose an empirical dc model for EGFETs, which can describe the behavior of the EGFETs smoothly and accurately over all regimes. The proposed model, built by extending the Enz-Krummenacher-Vittoz model, can also be used to model process variations, which was not possible previously due to fixed parameters for near threshold regime. It offers a single model for all the operating regions of the transistors with only one equation for the drain current. Additionally, it models the transistors with a less number of parameters but higher accuracy compared with existing techniques. Measurement results from several fabricated EGFETs confirm that the proposed model can predict the I-V more accurately compared with the state-of-the-art models in all operating regions. Additionally, the measurements on the frequency of a fabricated ring oscillator are only 4.7% different from the simulation results based on the proposed model using values for the switching capacitances extracted from measurement data, which shows more than 2× improvement compared with the state-of-the-art model.
Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface
(2018)
Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this paper, we present design details of a programmable passive SoC in compliance with ISO 15693/NFC5 standard for biomedical applications. The integrated system consists of a 32-bit microcontroller, a sensor readout circuit, a 12-bit SAR type ADC, 16 kB RAM, 16 kB ROM and other digital peripherals. The design is implemented in a 0.18 µm CMOS technology and used a die area of 1.52 mm × 3.24 mm. The simulated maximum power consumption of the analog block is 592 µW. The number of external components required by the SoC is limited to an external memory device, sensors, antenna and some passive components. The external memory device contains the application specific firmware. Based on the application, the firmware can be modified accordingly. The SoC design is suitable for medical implants to measure physiological parameters like temperature, pressure or ECG. As an application example, the authors have proposed a bioimplant to measure arterial blood pressure for patients suffering from Peripheral Artery Disease (PAD).
Printed Electronics (PE) is a promising technology that provides mechanical flexibility and low-cost fabrication. These features make PE the key enabler for emerging applications, such as smart sensors, wearables, and Internet of Things (IoTs). Since these applications need secure communication and/or authentication, it is vital to utilize security primitives for cryptographic key and identification. Physical Unclonable Functions (PUF) have been adopted widely to provide the secure keys. In this work, we present a weak PUF based on Electrolyte-gated FETs using inorganic inkjet printed electronics. A comprehensive analysis framework including Monte Carlo simulations based on real device measurements is developed to evaluate the proposed PE-PUF. Moreover, a multi-bit PE-PUF design is proposed to optimize area usage. The analysis results show that the PE-PUF has ideal uniqueness, good reliability, and can operates at low voltage which is critical for low-power PE applications. In addition, the proposed multi-bit PE-PUF reduces the area usage around 30%.
Uncontrollable manufacturing variations in electrical hardware circuits can be exploited as Physical Unclonable Functions (PUFs). Herein, we present a Printed Electronics (PE)-based PUF system architecture. Our proposed Differential Circuit PUF (DiffC-PUF) is a hybrid system, combining silicon-based and PE-based electronic circuits. The novel approach of the DiffC-PUF architecture is to provide a specially designed real hardware system architecture, that enables the automatic readout of interchangeable printed DiffC-PUF core circuits. The silicon-based addressing and evaluation circuit supplies and controls the printed PUF core and ensures seamless integration into silicon-based smart systems. Major objectives of our work are interconnected applications for the Internet of Things (IoT).
Printed electronics offers certain technological advantages over its silicon based counterparts, such as mechanical flexibility, low process temperatures, maskless and additive manufacturing process, leading to extremely low cost manufacturing. However, to be exploited in applications such as smart sensors, Internet of Things and wearables, it is essential that the printed devices operate at low supply voltages. Electrolyte gated field effect transistors (EGFETs) using solution-processed inorganic materials which are fully printed using inkjet printers at low temperatures are very promising candidates to provide such solutions. In this paper, we discuss the technology, process, modeling, fabrication, and design aspect of circuits based on EGFETs. We show how the measurements performed in the lab can accurately be modeled in order to be integrated in the design automation tool flow in the form of a Process Design Kit (PDK). We also review some of the remaining challenges in this technology and discuss our future directions to address them.
Electrolyte-gated transistors (EGTs) represent an interesting alternative to conventional dielectric-gating to reduce the required high supply voltage for printed electronic applications. Here, a type of ink-jet printable ion-gel is introduced and optimized to fabricate a chemically crosslinked ion-gel by self-assembled gelation, without additional crosslinking processes, e.g., UV-curing. For the self-assembled gelation, poly(vinyl alcohol) and poly(ethylene-alt-maleic anhydride) are used as the polymer backbone and chemical crosslinker, respectively, and 1-ethyl-3-methylimidazolium trifluoromethanesulfonate ([EMIM][OTf]) is utilized as an ionic species to ensure ionic conductivity. The as-synthesized ion-gel exhibits an ionic conductivity of ≈5 mS cm−1 and an effective capacitance of 5.4 µF cm−2 at 1 Hz. The ion-gel is successfully employed in EGTs with an indium oxide (In2O3) channel, which shows on/off-ratios of up to 1.3 × 106 and a subthreshold swing of 80.62 mV dec−1.
A physical unclonable function (PUF) is a hardware circuit that produces a random sequence based on its manufacturing-induced intrinsic characteristics. In the past decade, silicon-based PUFs have been extensively studied as a security primitive for identification and authentication. The emerging field of printed electronics (PE) enables novel application fields in the scope of the Internet of Things (IoT) and smart sensors. In this paper, we design and evaluate a printed differential circuit PUF (DiffC-PUF). The simulation data are verified by Monte Carlo analysis. Our design is highly scalable while consisting of a low number of printed transistors. Furthermore, we investigate the best operating point by varying the PUF challenge configuration and analyzing the PUF security metrics in order to achieve high robustness. At the best operating point, the results show areliability of 98.37% and a uniqueness of 50.02%, respectively. This analysis also provides useful and comprehensive insights into the design of hybrid or fully printed PUF circuits. In addition, the proposed printed DiffC-PUF core has been fabricated with electrolyte-gated field-effect transistor technology to verify our design in hardware.
Printed electronics can benefit from the deployment of electrolytesas gate insulators,which enables a high gate capacitance per unit area (1–10 μFcm−2) due to the formation of electrical double layers (EDLs). Consequently, electrolyte-gated field-effect transistors (EGFETs) attain high-charge carrier densities already in the subvoltage regime, allowing for low-voltage operation of circuits and systems. This article presents a systematic study of lumped terminal capacitances of printed electrolyte-gated transistors under various dc bias conditions. We perform voltage-dependent impedancemeasurements and separate extrinsic components from the lumped terminal capacitance.
The proposed Meyer-like capacitance model, which also accounts for the nonquasi-static (NQS) effect, agrees well with experimental data. Finally, to verify the model, we implement it in Verilog-A and simulate the transient response of an inverter and a ring oscillator circuit. Simulation results are in good agreement with the measurement data of fabricated devices.
Printed systems spark immense interest in industry, and for several parts such as solar cells or radio frequency identification antennas, printed products are already available on the market. This has led to intense research; however, printed field-effect transistors (FETs) and logics derived thereof still have not been sufficiently developed to be adapted by industry. Among others, one of the reasons for this is the lack of control of the threshold voltage during production. In this work, we show an approach to adjust the threshold voltage (Vth) in printed electrolyte-gated FETs (EGFETs) with high accuracy by doping indium-oxide semiconducting channels with chromium. Despite high doping concentrations achieved by a wet chemical process during precursor ink preparation, good on/off-ratios of more than five orders of magnitude could be demonstrated. The synthesis process is simple, inexpensive, and easily scalable and leads to depletion-mode EGFETs, which are fully functional at operation potentials below 2 V and allows us to increase Vth by approximately 0.5 V.
Development of Fully Printed Oxide Field-Effect Transistors using Graphene Passive Structures
(2019)
During the past decade to the present time, the topic of printed electronics has gained a lot of attention for their potential use in a number of practical applications, including biosensors, photovoltaic devices, RFIDs, flexible displays, large-area circuits, and so on. To fully realize printed electronic components and devices, effective techniques for the printing of passive structures and electrically and chemically compatible materials in the printed devices need to be developed first. The opportunity of using electrically conducting graphene inks will enable the integration of passive structures into active devices, as for example, printed electrolyte-gated transistors (EGTs). Accordingly, in this study, we present the parametric results obtained on fully printed electrolyte-gated transistors having graphene as the passive electrodes, an inorganic oxide semiconductor as the active channel, and a composite solid polymer electrolyte (CSPE) as the gate insulating material. This configuration offers high chemical and electrical stability while at the same time allowing EGT operation at low potentials, implying the distinct advantage of operation at low input voltages. The printed in-plane EGTs we developed exhibit excellent performance with device mobility up to 16 cm2 V–1 s–1, an ION/IOFF ratio of 105, and a subthreshold slope of 120 mV dec–1.