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Uncontrollable manufacturing variations in electrical hardware circuits can be exploited as Physical Unclonable Functions (PUFs). Herein, we present a Printed Electronics (PE)-based PUF system architecture. Our proposed Differential Circuit PUF (DiffC-PUF) is a hybrid system, combining silicon-based and PE-based electronic circuits. The novel approach of the DiffC-PUF architecture is to provide a specially designed real hardware system architecture, that enables the automatic readout of interchangeable printed DiffC-PUF core circuits. The silicon-based addressing and evaluation circuit supplies and controls the printed PUF core and ensures seamless integration into silicon-based smart systems. Major objectives of our work are interconnected applications for the Internet of Things (IoT).
Covert- and side-channels as well as techniques to establish them in cloud computing are in focus of research for quite some time. However, not many concrete mitigation methods have been developed and even less have been adapted and concretely implemented by cloud providers. Thus, we recently conceptually proposed C 3 -Sched a CPU scheduling based approach to mitigate L2 cache covert-channels. Instead of flushing the cache on every context switch, we schedule trusted virtual machines to create noise which prevents potential covert-channels. Additionally, our approach aims on preserving performance by utilizing existing instead of artificial workload while reducing covert-channel related cache flushes to cases where not enough noise has been achieved. In this work we evaluate cache covert-channel mitigation and performance impact of our integration of C 3 -Sched in the XEN credit scheduler. Moreover, we compare it to naive solutions and more competitive approaches.
The CAN bus still is an important fieldbus in various domains, e.g. for in-car communication or automation applications. To counter security threats and concerns in such scenarios we design, implement, and evaluate the use of an end-to-end security concept based on the Transport Layer Security protocol. It is used to establish authenticated, integrity-checked, and confidential communication channels between field devices connected via CAN. Our performance measurements show that it is possible to use TLS at least for non time-critical applications, as well as for generic embedded networks.
Cell lifetime diagnostics and system be-havior of stationary LFP/graphite lithium-ion batteries
(2018)
Implementierung von Softcore-Prozessoren und/oder weiteren IPs (Intellectual Property) in FPGAs
(2018)
Die zunehmende Integration von kompletten Systemen auf einem Chip (System-on-Chip, SoC) erfordert auch immer die Integration einer Recheneinheit bzw. eines Prozessorkerns. Möchte man insbesondere Low-Power-SoC-Systeme entwickeln, z.B. drahtlose Sensor-SoC-Systeme für Anwendungen im Rahmen von Industrie 4.0, ist die Implementierung eines solchen Prozessorkerns mit hohen Herausforderungen verbunden. Prinzipiell können hierfür verschiedene Ansätze verfolgt werden, nämlich die Implementierung einer Hardcore Prozessor-IP (IP = Intellectual Property) oder einer Softcore-Prozessor-IP. Im vorliegenden Beitrag wird zunächst auf den derzeitigen Stand der Technik verfügbarer Hardcore- oder Softcore-Prozessoren unter den Randbedingungen der Low-Power-Anforderungen und der weiten Verbreitung des Cores in industriellen Anwendungen eingegangen. Schließlich werden die Ergebnisse der Implementierung und Evaluierung eines derzeit frei verfügbaren 16-bit MSP430-kompatiblen Softcore Prozessors auf einem Altera-Cyclon-FPGA vorgestellt. Aus den Ergebnissen wird ein entsprechendes Fazit für die Implementierung von Low-Power-SoC-Systeme gegeben.
Dieser Beitrag stellt die Möglichkeiten des 3D-Druckes unter der Berücksichtigung von Mensch-Roboter-Kollaborations-Anforderungen dar. Dabei werden die Vorteile mit besonderem Fokus auf die zusätzliche Gestaltungsfreiheit erläutert. Anhand von Beispielen wird der Stand der Technik bereits eingesetzter Sensorik sowie deren Notwendigkeit in Greifsystemen erläutert. Im weiteren Verlauf dieses Beitrags werden allgemeine Verfahren für die additive Verarbeitung von leitfähigen Materialien vorgestellt. Daran angeknüpft sind Beispiele speziell zur 3D-gedruckten Sensorik. Abgerundet wird der Beitrag mit einem Ausblick bezüglich 3D-gedruckter Sensorik in MRK-Greifsystemen.
The Transport Layer Security (TLS) protocol is a cornerstone of secure network communication, not only for online banking, e-commerce, and social media, but also for industrial communication and cyber-physical systems. Unfortunately, implementing TLS correctly is very challenging, as becomes evident by considering the high frequency of bugfixes filed for many TLS implementations. Given the high significance of TLS, advancing the quality of implementations is a sustained pursuit. We strive to support these efforts by presenting a novel, response-distribution guided fuzzing algorithm for differential testing of black-box TLS implementations. Our algorithm generates highly diverse and mostly-valid TLS stimulation messages, which evoke more behavioral discrepancies in TLS server implementations than other algorithms. We evaluate our algorithm using 37 different TLS implementations and discuss―by means of a case study―how the resulting data allows to assess and improve not only implementations of TLS but also to identify underspecified corner cases. We introduce suspiciousness as a per-implementation metric of anomalous implementation behavior and find that more recent or bug-fixed implementations tend to have a lower suspiciousness score. Our contribution is complementary to existing tools and approaches in the area, and can help reveal implementation flaws and avoid regression. While being presented for TLS, we expect our algorithm's guidance scheme to be applicable and useful also in other contexts. Source code and data is made available for fellow researchers in order to stimulate discussions and invite others to benefit from and advance our work.