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Printed electronics (PE) is a fast-growing field with promising applications in wearables, smart sensors, and smart cards, since it provides mechanical flexibility, and low-cost, on-demand, and customizable fabrication. To secure the operation of these applications, true random number generators (TRNGs) are required to generate unpredictable bits for cryptographic functions and padding. However, since the additive fabrication process of the PE circuits results in high intrinsic variations due to the random dispersion of the printed inks on the substrate, constructing a printed TRNG is challenging. In this article, we exploit the additive customizable fabrication feature of inkjet printing to design a TRNG based on electrolyte-gated field-effect transistors (EGFETs). We also propose a printed resistor tuning flow for the TRNG circuit to mitigate the overall process variation of the TRNG so that the generated bits are mostly based on the random noise in the circuit, providing a true random behavior. The simulation results show that the overall process variation of the TRNGs is mitigated by 110 times, and the generated bitstream of the tuned TRNGs passes the National Institute of Standards and Technology - Statistical Test Suite. For the proof of concept, the proposed TRNG circuit was fabricated and tuned. The characterization results of the tuned TRNGs prove that the TRNGs generate random bitstreams at the supply voltage of down to 0.5 V. Hence, the proposed TRNG design is suitable to secure low-power applications in this domain.
Advances in printed electronics (PE) enables new applications, particularly in ultra-low-cost domains. However, achieving high-throughput printing processes and manufacturing yield is one of the major challenges in the large-scale integration of PE technology. In this article, we present a programmable printed circuit based on an efficient printed lookup table (pLUT) to address these challenges by combining the advantages of the high-throughput advanced printing and maskless point-of-use final configuration printing. We propose a novel pLUT design which is more efficient in PE realization compared to existing LUT designs. The proposed pLUT design is simulated, fabricated, and programmed as different logic functions with inkjet printed conductive ink to prove that it can realize digital circuit functionality with the use of programmability features. The measurements show that the fabricated LUT design is operable at 1 V.
Printed electronics (PE) enables disruptive applications in wearables, smart sensors, and healthcare since it provides mechanical flexibility, low cost, and on-demand fabrication. The progress in PE raises trust issues in the supply chain and vulnerability to reverse engineering (RE) attacks. Recently, RE attacks on PE circuits have been successfully performed, pointing out the need for countermeasures against RE, such as camouflaging. In this article, we propose a printed camouflaged logic cell that can be inserted into PE circuits to thwart RE. The proposed cell is based on three components achieved by changing the fabrication process that exploits the additive manufacturing feature of PE. These components are optically look-alike, while their electrical behaviors are different, functioning as a transistor, short, and open. The properties of the proposed cell and standard PE cells are compared in terms of voltage swing, delay, power consumption, and area. Moreover, the proposed camouflaged cell is fabricated and characterized to prove its functionality. Furthermore, numerous camouflaged components are fabricated, and their (in)distinguishability is assessed to validate their optical similarities based on the recent RE attacks on PE. The results show that the proposed cell is a promising candidate to be utilized in camouflaging PE circuits with negligible overhead.
A printed electronics technology has the advantage of additive and extremely low-cost fabrication compared with the conventional silicon technology. Specifically, printed electrolyte-gated field-effect transistors (EGFETs) are attractive for low-cost applications in the Internet-of-Things domain as they can operate at low supply voltages. In this paper, we propose an empirical dc model for EGFETs, which can describe the behavior of the EGFETs smoothly and accurately over all regimes. The proposed model, built by extending the Enz-Krummenacher-Vittoz model, can also be used to model process variations, which was not possible previously due to fixed parameters for near threshold regime. It offers a single model for all the operating regions of the transistors with only one equation for the drain current. Additionally, it models the transistors with a less number of parameters but higher accuracy compared with existing techniques. Measurement results from several fabricated EGFETs confirm that the proposed model can predict the I-V more accurately compared with the state-of-the-art models in all operating regions. Additionally, the measurements on the frequency of a fabricated ring oscillator are only 4.7% different from the simulation results based on the proposed model using values for the switching capacitances extracted from measurement data, which shows more than 2× improvement compared with the state-of-the-art model.
Rectifiersare vital electronic circuits for signal and power conversion in various smart sensor applications. The ability to process low input voltage levels, for example, from vibrational energy harvesters is a major challenge with existing passive rectifiers in printed electronics, stemming mainly from the built-in potential of the diode's p-njunction. To address this problem, in this work, we design, fabricate, and characterize an inkjet-printed full-wave rectifier using diode-connected electrolyte-gated thin-film transistors (EGTs). Using both experimental and simulation approaches, we investigate how the rectifier can benefit from the near-zero threshold voltage of transistors, which can be enabled by proper channel geometry setting in EGT technology. The presented circuit can be operated at 1-V input voltage, featuring a remarkably small voltage loss of 140 mV and a cutoff frequency of ~300 Hz. Below the cutoff frequency, more than 2.6-μW dc power is obtained over the load resistances ranging from 5 to 20 kQ. Furthermore, experiments show that the circuit can work with an input amplitude down to 500 mV. This feature makes the presented design highly suitable for a variety of energy-harvesting applications.
In many application domains, in particular automotives, guaranteeing a very low failure rate is crucial to meet functional and safety standards. Especially, reliable operation of memory components such as SRAM cells is of essential importance. Due to aggressive technology downscaling, process and runtime variations significantly impact manufacturing yield as well as functionality. For this reason, a thorough memory failure rate assessment is imperative for correct circuit operation and yield improvement. In this regard, Monte Carlo simulations have been used as the conventional method to estimate the variability induced failure rate of memory components. However, Monte Carlo methods become infeasible when estimating rare events such as high-sigma failure rates. To this end, Importance Sampling methods have been proposed which reduce the number of required simulations substantially. However, existing methods still suffer from inaccuracies and high computational efforts, in particular for high-sigma problems. In this paper, we fill this gap by presenting an efficient mixture Importance Sampling approach based on Bayesian optimization, which deploys a surface model of the objective function to find the most probable failure points. Its advantages include constant complexity independent of the dimensions of design space, the potential to find the global extrema, and higher trustworthiness of the estimated failure rate by accurately exploring the design space. The approach is evaluated on a 6T-SRAM cell as well as a master-slave latch based on a 28nm FDSOI process. The results show an improvement in accuracy, resulting in up to 63× better accuracy in estimating failure rates compared to the best state-of-the-art solutions on a 28nm technology node.
Printed Electronics technology is a key-enabler for smart sensors, soft robotics, and wearables. The inkjet printed electrolyte-gated field effect transistor (EGFET) technology is a promising candidate for such applications due to its low-power operation, high field-effect mobility, and on-demand fabrication. Unlike conventional silicon-based technologies, inkjet printed electronics technology is an additive manufacturing process where multiple layers are printed on top of each other to realize functional devices such as transistors and their interconnections. Due to the additive manufacturing process, the technology has limited routing layers. For routing of complex circuits, insulating crossovers are printed at the intersection of routing paths to isolate them. The crossover can alter the electrical properties of a circuit based on specific location on a routing path. In this work, we propose a crossover-aware placement and routing (COPnR) methodology for inkjet-printed circuits by integrating the crossover constraints in our design framework. Our proposed placement methodology is based on a state-of-the-art evolutionary algorithm while the routing optimization is done using a genetic algorithm. The proposed methodology is compared with the industrial standard placement and routing (PnR) tools. On average, the proposed methodology has 38% fewer crossovers and 94% fewer failing paths compared to the industrial PnR tools applied to printed circuit designs.
A physical unclonable function (PUF) is a hardware circuit that produces a random sequence based on its manufacturing-induced intrinsic characteristics. In the past decade, silicon-based PUFs have been extensively studied as a security primitive for identification and authentication. The emerging field of printed electronics (PE) enables novel application fields in the scope of the Internet of Things (IoT) and smart sensors. In this paper, we design and evaluate a printed differential circuit PUF (DiffC-PUF). The simulation data are verified by Monte Carlo analysis. Our design is highly scalable while consisting of a low number of printed transistors. Furthermore, we investigate the best operating point by varying the PUF challenge configuration and analyzing the PUF security metrics in order to achieve high robustness. At the best operating point, the results show areliability of 98.37% and a uniqueness of 50.02%, respectively. This analysis also provides useful and comprehensive insights into the design of hybrid or fully printed PUF circuits. In addition, the proposed printed DiffC-PUF core has been fabricated with electrolyte-gated field-effect transistor technology to verify our design in hardware.
Embedded Analog Physical Unclonable Function System to Extract Reliable and Unique Security Keys
(2020)
Internet of Things (IoT) enabled devices have become more and more pervasive in our everyday lives. Examples include wearables transmitting and processing personal data and smart labels interacting with customers. Due to the sensitive data involved, these devices need to be protected against attackers. In this context, hardware-based security primitives such as Physical Unclonable Functions (PUFs) provide a powerful solution to secure interconnected devices. The main benefit of PUFs, in combination with traditional cryptographic methods, is that security keys are derived from the random intrinsic variations of the underlying core circuit. In this work, we present a holistic analog-based PUF evaluation platform, enabling direct access to a scalable design that can be customized to fit the application requirements in terms of the number of required keys and bit width. The proposed platform covers the full software and hardware implementations and allows for tracing the PUF response generation from the digital level back to the internal analog voltages that are directly involved in the response generation procedure. Our analysis is based on 30 fabricated PUF cores that we evaluated in terms of PUF security metrics and bit errors for various temperatures and biases. With an average reliability of 99.20% and a uniqueness of 48.84%, the proposed system shows values close to ideal.