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A physical unclonable function (PUF) is a hardware circuit that produces a random sequence based on its manufacturing-induced intrinsic characteristics. In the past decade, silicon-based PUFs have been extensively studied as a security primitive for identification and authentication. The emerging field of printed electronics (PE) enables novel application fields in the scope of the Internet of Things (IoT) and smart sensors. In this paper, we design and evaluate a printed differential circuit PUF (DiffC-PUF). The simulation data are verified by Monte Carlo analysis. Our design is highly scalable while consisting of a low number of printed transistors. Furthermore, we investigate the best operating point by varying the PUF challenge configuration and analyzing the PUF security metrics in order to achieve high robustness. At the best operating point, the results show areliability of 98.37% and a uniqueness of 50.02%, respectively. This analysis also provides useful and comprehensive insights into the design of hybrid or fully printed PUF circuits. In addition, the proposed printed DiffC-PUF core has been fabricated with electrolyte-gated field-effect transistor technology to verify our design in hardware.
In many application domains, in particular automotives, guaranteeing a very low failure rate is crucial to meet functional and safety standards. Especially, reliable operation of memory components such as SRAM cells is of essential importance. Due to aggressive technology downscaling, process and runtime variations significantly impact manufacturing yield as well as functionality. For this reason, a thorough memory failure rate assessment is imperative for correct circuit operation and yield improvement. In this regard, Monte Carlo simulations have been used as the conventional method to estimate the variability induced failure rate of memory components. However, Monte Carlo methods become infeasible when estimating rare events such as high-sigma failure rates. To this end, Importance Sampling methods have been proposed which reduce the number of required simulations substantially. However, existing methods still suffer from inaccuracies and high computational efforts, in particular for high-sigma problems. In this paper, we fill this gap by presenting an efficient mixture Importance Sampling approach based on Bayesian optimization, which deploys a surface model of the objective function to find the most probable failure points. Its advantages include constant complexity independent of the dimensions of design space, the potential to find the global extrema, and higher trustworthiness of the estimated failure rate by accurately exploring the design space. The approach is evaluated on a 6T-SRAM cell as well as a master-slave latch based on a 28nm FDSOI process. The results show an improvement in accuracy, resulting in up to 63× better accuracy in estimating failure rates compared to the best state-of-the-art solutions on a 28nm technology node.
Emerging applications in soft robotics, wearables, smart consumer products or IoT-devices benefit from soft materials, flexible substrates in conjunction with electronic functionality. Due to high production costs and conformity restrictions, rigid silicon technologies do not meet application requirements in these new domains. However, whenever signal processing becomes too comprehensive, silicon technology must be used for the high-performance computing unit. At the same time, designing everything in flexible or printed electronics using conventional digital logic is not feasible yet due to the limitations of printed technologies in terms of performance, power and integration density. We propose to rather use the strengths of neuromorphic computing architectures consisting in their homogeneous topologies, few building blocks and analog signal processing to be mapped to an inkjet-printed hardware architecture. It has remained a challenge to demonstrate non-linear elements besides weighted aggregation. We demonstrate in this work printed hardware building blocks such as inverter-based comprehensive weight representation and resistive crossbars as well as printed transistor-based activation functions. In addition, we present a learning algorithm developed to train the proposed printed NCS architecture based on specific requirements and constraints of the technology.
Morphological transition of a rod-shaped phase into a string of spherical particles is commonly observed in the microstructures of alloys during solidification (Ratke and Mueller, 2006). This transition phenomenon can be explained by the classic Plateau-Rayleigh theory which was derived for fluid jets based on the surface area minimization principle. The quintessential work of Plateau-Rayleigh considers tiny perturbations (amplitude much less than the radius) to the continuous phase and for large amplitude perturbations, the breakup condition for the rod-shaped phase is still a knotty issue. Here, we present a concise thermodynamic model based on the surface area minimization principle as well as a non-linear stability analysis to generalize Plateau-Rayleigh’s criterion for finite amplitude perturbations. Our results demonstrate a breakup transition from a continuous phase via dispersed particles towards a uniform-radius cylinder, which has not been found previously, but is observed in our phase-field simulations. This new observation is attributed to a geometric constraint, which was overlooked in former studies. We anticipate that our results can provide further insights on microstructures with spherical particles and cylinder-shaped phases.
Amorphous In-Ga-Zn-O (IGZO) is a high-mobility semiconductor employed in modern thin-film transistors for displays and it is considered as a promising material for Schottky diode-based rectifiers. Properties of the electronic components based on IGZO strongly depend on the manufacturing parameters such as the oxygen partial pressure during IGZO sputtering and post-deposition thermal annealing. In this study, we investigate the combined effect of sputtering conditions of amorphous IGZO (In:Ga:Zn=1:1:1) and post-deposition thermal annealing on the properties of vertical thin-film Pt-IGZO-Cu Schottky diodes, and evaluated the applicability of the fabricated Schottky diodes for low-frequency half-wave rectifier circuits. The change of the oxygen content in the gas mixture from 1.64% to 6.25%, and post-deposition annealing is shown to increase the current rectification ratio from 10 5 to 10 7 at ±1 V, Schottky barrier height from 0.64 eV to 0.75 eV, and the ideality factor from 1.11 to 1.39. Half-wave rectifier circuits based on the fabricated Schottky diodes were simulated using parameters extracted from measured current-voltage and capacitance-voltage characteristics. The half-wave rectifier circuits were realized at 100 kHz and 300 kHz on as-fabricated Schottky diodes with active area of 200 μm × 200 μm, which is relevant for the near-field communication (125 kHz - 134 kHz), and provided the output voltage amplitude of 0.87 V for 2 V supply voltage. The simulation results matched with the measurement data, verifying the model accuracy for circuit level simulation.
Silicon (Si) has turned out to be a promising active material for next‐generation lithium‐ion battery anodes. Nevertheless, the issues known from Si as electrode material (pulverization effects, volume change etc.) are impeding the development of Si anodes to reach market maturity. In this study, we are investigating a possible application of Si anodes in low‐power printed electronic applications. Tailored Si inks are produced and the impact of carbon coating on the printability and their electrochemical behavior as printed Si anodes is investigated. The printed Si anodes contain active material loadings that are practical for powering printed electronic devices, like electrolyte gated transistors, and are able to show high capacity retentions. A capacity of 1754 mAh/gSi is achieved for a printed Si anode after 100 cycles. Additionally, the direct applicability of the printed Si anodes is shown by successfully powering an ink‐jet printed transistor.
Fully Printed Inverters using Metal‐Oxide Semiconductor and Graphene Passives on Flexible Substrates
(2020)
Printed and flexible metal‐oxide transistor technology has recently demonstrated great promise due to its high performance and robust mechanical stability. Herein, fully printed inverter structures using electrolyte‐gated oxide transistors on a flexible polyimide (PI) substrate are discussed in detail. Conductive graphene ink is printed as the passive structures and interconnects. The additive printed transistors on PI substrates show an on/off ratio of 106 and show mobilities similar to the state‐of‐the‐art printed transistors on rigid substrates. Printed meander structures of graphene are used as pull‐up resistances in a transistor–resistor logic to create fully printed inverters. The printed and flexible inverters show a signal gain of 3.5 and a propagation delay of 30 ms. These printed inverters are able to withstand a tensile strain of 1.5% following more than 200 cycles of mechanical bending. The stability of the electrical direct current (DC) properties has been observed over a period of 5 weeks. These oxide transistor‐based fully printed inverters are relevant for digital printing methods which could be implemented into roll‐to‐roll processes.
Development of Fully Printed Oxide Field-Effect Transistors using Graphene Passive Structures
(2019)
During the past decade to the present time, the topic of printed electronics has gained a lot of attention for their potential use in a number of practical applications, including biosensors, photovoltaic devices, RFIDs, flexible displays, large-area circuits, and so on. To fully realize printed electronic components and devices, effective techniques for the printing of passive structures and electrically and chemically compatible materials in the printed devices need to be developed first. The opportunity of using electrically conducting graphene inks will enable the integration of passive structures into active devices, as for example, printed electrolyte-gated transistors (EGTs). Accordingly, in this study, we present the parametric results obtained on fully printed electrolyte-gated transistors having graphene as the passive electrodes, an inorganic oxide semiconductor as the active channel, and a composite solid polymer electrolyte (CSPE) as the gate insulating material. This configuration offers high chemical and electrical stability while at the same time allowing EGT operation at low potentials, implying the distinct advantage of operation at low input voltages. The printed in-plane EGTs we developed exhibit excellent performance with device mobility up to 16 cm2 V–1 s–1, an ION/IOFF ratio of 105, and a subthreshold slope of 120 mV dec–1.
Embedded Analog Physical Unclonable Function System to Extract Reliable and Unique Security Keys
(2020)
Internet of Things (IoT) enabled devices have become more and more pervasive in our everyday lives. Examples include wearables transmitting and processing personal data and smart labels interacting with customers. Due to the sensitive data involved, these devices need to be protected against attackers. In this context, hardware-based security primitives such as Physical Unclonable Functions (PUFs) provide a powerful solution to secure interconnected devices. The main benefit of PUFs, in combination with traditional cryptographic methods, is that security keys are derived from the random intrinsic variations of the underlying core circuit. In this work, we present a holistic analog-based PUF evaluation platform, enabling direct access to a scalable design that can be customized to fit the application requirements in terms of the number of required keys and bit width. The proposed platform covers the full software and hardware implementations and allows for tracing the PUF response generation from the digital level back to the internal analog voltages that are directly involved in the response generation procedure. Our analysis is based on 30 fabricated PUF cores that we evaluated in terms of PUF security metrics and bit errors for various temperatures and biases. With an average reliability of 99.20% and a uniqueness of 48.84%, the proposed system shows values close to ideal.
Hybrid low-voltage physical unclonable function based on inkjet-printed metal-oxide transistors
(2020)
Modern society is striving for digital connectivity that demands information security. As an emerging technology, printed electronics is a key enabler for novel device types with free form factors, customizability, and the potential for large-area fabrication while being seamlessly integrated into our everyday environment. At present, information security is mainly based on software algorithms that use pseudo random numbers. In this regard, hardware-intrinsic security primitives, such as physical unclonable functions, are very promising to provide inherent security features comparable to biometrical data. Device-specific, random intrinsic variations are exploited to generate unique secure identifiers. Here, we introduce a hybrid physical unclonable function, combining silicon and printed electronics technologies, based on metal oxide thin film devices. Our system exploits the inherent randomness of printed materials due to surface roughness, film morphology and the resulting electrical characteristics. The security primitive provides high intrinsic variation, is non-volatile, scalable and exhibits nearly ideal uniqueness.
A Hybrid Optoelectronic Sensor Platform with an Integrated Solution‐Processed Organic Photodiode
(2021)
Hybrid systems, unifying printed electronics with silicon‐based technology, can be seen as a driving force for future sensor development. Especially interesting are sensing elements based on printed devices in combination with silicon‐based high‐performance electronics for data acquisition and communication. In this work, a hybrid system integrating a solution‐processed organic photodiode in a silicon‐based system environment, which enables flexible device measurement and application‐driven development, is presented. For performance evaluation of the integrated organic photodiode, the measurements are compared to a silicon‐based counterpart. Therefore, the steady state response of the hybrid system is presented. Promising application scenarios are described, where a solution‐processed organic photodiode is fully integrated in a silicon system.
Effective medium theories (EMT) are powerful tools to calculate sample averaged thermoelectric material properties of composite materials. However, averaging over the heterogeneous spatial distribution of the phases can lead to incorrect estimates of the thermoelectric transport properties and the figure of merit ZT in compositions close to the percolation threshold. This is particularly true when the phases’ electronic properties are rather distinct leading to pronounced percolation effects. The authors propose an alternative model to calculate the thermoelectric properties of multi‐phased materials that are based on an expanded nodal analysis of random resistor networks (RRN). This method conserves the information about the morphology of the individual phases, allowing the study of the current paths through the phases and the influence of heterogeneous charge transport and cluster formation on the effective material properties of the composite. The authors show that in composites with strongly differing phases close to the percolation threshold the thermoelectric properties and the ZT value are always dominated exclusively by one phase or the other and never by an average of both. For these compositions, the individual samples display properties vastly different from EMT predictions and can be exploited for an increased thermoelectric performance.
Printed Electronics technology is a key-enabler for smart sensors, soft robotics, and wearables. The inkjet printed electrolyte-gated field effect transistor (EGFET) technology is a promising candidate for such applications due to its low-power operation, high field-effect mobility, and on-demand fabrication. Unlike conventional silicon-based technologies, inkjet printed electronics technology is an additive manufacturing process where multiple layers are printed on top of each other to realize functional devices such as transistors and their interconnections. Due to the additive manufacturing process, the technology has limited routing layers. For routing of complex circuits, insulating crossovers are printed at the intersection of routing paths to isolate them. The crossover can alter the electrical properties of a circuit based on specific location on a routing path. In this work, we propose a crossover-aware placement and routing (COPnR) methodology for inkjet-printed circuits by integrating the crossover constraints in our design framework. Our proposed placement methodology is based on a state-of-the-art evolutionary algorithm while the routing optimization is done using a genetic algorithm. The proposed methodology is compared with the industrial standard placement and routing (PnR) tools. On average, the proposed methodology has 38% fewer crossovers and 94% fewer failing paths compared to the industrial PnR tools applied to printed circuit designs.
A printed electronics technology has the advantage of additive and extremely low-cost fabrication compared with the conventional silicon technology. Specifically, printed electrolyte-gated field-effect transistors (EGFETs) are attractive for low-cost applications in the Internet-of-Things domain as they can operate at low supply voltages. In this paper, we propose an empirical dc model for EGFETs, which can describe the behavior of the EGFETs smoothly and accurately over all regimes. The proposed model, built by extending the Enz-Krummenacher-Vittoz model, can also be used to model process variations, which was not possible previously due to fixed parameters for near threshold regime. It offers a single model for all the operating regions of the transistors with only one equation for the drain current. Additionally, it models the transistors with a less number of parameters but higher accuracy compared with existing techniques. Measurement results from several fabricated EGFETs confirm that the proposed model can predict the I-V more accurately compared with the state-of-the-art models in all operating regions. Additionally, the measurements on the frequency of a fabricated ring oscillator are only 4.7% different from the simulation results based on the proposed model using values for the switching capacitances extracted from measurement data, which shows more than 2× improvement compared with the state-of-the-art model.
Printed systems spark immense interest in industry, and for several parts such as solar cells or radio frequency identification antennas, printed products are already available on the market. This has led to intense research; however, printed field-effect transistors (FETs) and logics derived thereof still have not been sufficiently developed to be adapted by industry. Among others, one of the reasons for this is the lack of control of the threshold voltage during production. In this work, we show an approach to adjust the threshold voltage (Vth) in printed electrolyte-gated FETs (EGFETs) with high accuracy by doping indium-oxide semiconducting channels with chromium. Despite high doping concentrations achieved by a wet chemical process during precursor ink preparation, good on/off-ratios of more than five orders of magnitude could be demonstrated. The synthesis process is simple, inexpensive, and easily scalable and leads to depletion-mode EGFETs, which are fully functional at operation potentials below 2 V and allows us to increase Vth by approximately 0.5 V.
In this report, we have studied field-effect transistors (FETs) using low-density alumina for electrolytic gating. Device layers have been prepared starting from the structured ITO glasses by printing the In 2 O 3 channels, low-temperature atomic layer deposition (ALD) of alumina (Al 2 O 3 ), and printing graphene top gates. The transistor performance could be deliberately changed by alternating the ambient humidity; furthermore, ID,ON/ID,OFF-ratios of up to seven orders of magnitude and threshold voltages between 0.66 and 0.43 V, decreasing with an increasing relative humidity between 40% and 90%, could be achieved. In contrast to the common usage of Al 2 O 3 as the dielectric in the FETs, our devices show electrolyte-typegating behavior. This is a result from the formation of protons on the Al 2 O 3 surfaces at higher humidities. Due to the very high local capacitances of the Helmholtz double layers at the channel surfaces, the operation voltage can be as low as 1 V. At low humidities (≤30%), the solid electrolyte dries out and the performance breaks down; however, it can fully reversibly be regained upon a humidity increase. Using ALD-derived alumina as solid electrolyte gating material, thus, allows low-voltage operation and provides a chemically stable gating material while maintaining low process temperatures. However, it has proven to be highly humidity-dependent in its performance.
High-performance Ag–Se-based n-type printed thermoelectric (TE) materials suitable for room-temperature applications have been developed through a new and facile synthesis approach. A high magnitude of the Seebeck coefficient up to 220 μV K–1 and a TE power factor larger than 500 μW m–1 K–2 for an n-type printed film are achieved. A high figure-of-merit ZT ∼0.6 for a printed material has been found in the film with a low in-plane thermal conductivity κF of ∼0.30 W m–1 K–1. Using this material for n-type legs, a flexible folded TE generator (flexTEG) of 13 thermocouples has been fabricated. The open-circuit voltage of the flexTEG for temperature differences of ΔT = 30 and 110 K is found to be 71.1 and 181.4 mV, respectively. Consequently, very high maximum output power densities pmax of 6.6 and 321 μW cm–2 are estimated for the temperature difference of ΔT = 30 K and ΔT = 110 K, respectively. The flexTEG has been demonstrated by wearing it on the lower wrist, which resulted in an output voltage of ∼72.2 mV for ΔT ≈ 30 K. Our results pave the way for widespread use in wearable devices.
In this study, a facile method to fabricate a cohesive ion‐gel based gate insulator for electrolyte‐gated transistors is introduced. The adhesive and flexible ion‐gel can be laminated easily on the semiconducting channel and electrode manually by hand. The ion‐gel is synthesized by a straightforward technique without complex procedures and shows a remarkable ionic conductivity of 4.8 mS cm−1 at room temperature. When used as a gate insulator in electrolyte‐gated transistors (EGTs), an on/off current ratio of 2.24×104 and a subthreshold swing of 117 mV dec−1 can be achieved. This performance is roughly equivalent to that of ink drop‐casted ion‐gels in electrolyte‐gated transistors, indicating that the film‐attachment method might represent a valuable alternative to ink drop‐casting for the fabrication of gate insulators.
Electrolyte-gated transistors (EGTs) represent an interesting alternative to conventional dielectric-gating to reduce the required high supply voltage for printed electronic applications. Here, a type of ink-jet printable ion-gel is introduced and optimized to fabricate a chemically crosslinked ion-gel by self-assembled gelation, without additional crosslinking processes, e.g., UV-curing. For the self-assembled gelation, poly(vinyl alcohol) and poly(ethylene-alt-maleic anhydride) are used as the polymer backbone and chemical crosslinker, respectively, and 1-ethyl-3-methylimidazolium trifluoromethanesulfonate ([EMIM][OTf]) is utilized as an ionic species to ensure ionic conductivity. The as-synthesized ion-gel exhibits an ionic conductivity of ≈5 mS cm−1 and an effective capacitance of 5.4 µF cm−2 at 1 Hz. The ion-gel is successfully employed in EGTs with an indium oxide (In2O3) channel, which shows on/off-ratios of up to 1.3 × 106 and a subthreshold swing of 80.62 mV dec−1.
A versatile liquid metal (LM) printing process enabling the fabrication of various fully printed devices such as intra- and interconnect wires, resistors, diodes, transistors, and basic circuit elements such as inverters which are process compatible with other digital printing and thin film structuring methods for integration is presented. For this, a glass capillary-based direct-write method for printing LMs such as eutectic gallium alloys, exploring the potential for fully printed LM-enabled devices is demonstrated. Examples for successful device fabrication include resistors, p–n diodes, and field effect transistors. The device functionality and easiness of one integrated fabrication flow shows that the potential of LM printing is far exceeding the use of interconnecting conventional electronic devices in printed electronics.
Oxide semiconductors are highly promising candidates for the most awaited, next-generation electronics, namely, printed electronics. As a fabrication route for the solution-processed/printed oxide semiconductors, photonic curing is becoming increasingly popular, as compared to the conventional thermal curing method; the former offers numerous advantages over the latter, such as low process temperatures and short exposure time and thereby, high throughput compatibility. Here, using dissimilar photonic curing concepts (UV–visible light and UV-laser), we demonstrate facile fabrication of high performance In2O3 field-effect transistors (FETs). Beside the processing related issues (temperature, time etc.), the other known limitation of oxide electronics is the lack of high performance p-type semiconductors, which can be bypassed using unipolar logics from high mobility n-type semiconductors alone. Interestingly, here we have found that our chosen distinct photonic curing methods can offer a large variation in threshold voltage, when they are fabricated from the same precursor ink. Consequently, both depletion and enhancement-mode devices have been achieved which can be used as the pull-up and pull-down transistors in unipolar inverters. The present device fabrication recipe demonstrates fast processing of low operation voltage, high performance FETs with large threshold voltage tunability.
Rectifiersare vital electronic circuits for signal and power conversion in various smart sensor applications. The ability to process low input voltage levels, for example, from vibrational energy harvesters is a major challenge with existing passive rectifiers in printed electronics, stemming mainly from the built-in potential of the diode's p-njunction. To address this problem, in this work, we design, fabricate, and characterize an inkjet-printed full-wave rectifier using diode-connected electrolyte-gated thin-film transistors (EGTs). Using both experimental and simulation approaches, we investigate how the rectifier can benefit from the near-zero threshold voltage of transistors, which can be enabled by proper channel geometry setting in EGT technology. The presented circuit can be operated at 1-V input voltage, featuring a remarkably small voltage loss of 140 mV and a cutoff frequency of ~300 Hz. Below the cutoff frequency, more than 2.6-μW dc power is obtained over the load resistances ranging from 5 to 20 kQ. Furthermore, experiments show that the circuit can work with an input amplitude down to 500 mV. This feature makes the presented design highly suitable for a variety of energy-harvesting applications.
Electrolyte-gated, printed field-effect transistors exhibit high charge carrier densities in the channel and thus high on-currents at low operating voltages, allowing for the low-power operation of such devices. This behavior is due to the high area-specific capacitance of the device, in which the electrolyte takes the role of the dielectric layer of classical architectures. In this paper, we investigate intrinsic double-layer capacitances of ink-jet printed electrolyte-gated inorganic field-effect transistors in both in-plane and top-gate architectures by means of voltage-dependent impedance spectroscopy. By comparison with deembedding structures, we separate the intrinsic properties of the double-layer capacitance at the transistor channel from parasitic effects and deduce accurate estimates for the double-layer capacitance based on an equivalent circuit fitting. Based on these results, we have performed simulations of the electrolyte cutoff frequency as a function of electrolyte and gate resistances, showing that the top-gate architecture has the potential to reach the kilohertz regime with proper optimization of materials and printing process. Our findings additionally enable accurate modeling of the frequency-dependent capacitance of electrolyte/ion gel-gated devices as required in the small-signal analysis in the circuit simulation.
Printed electronics can benefit from the deployment of electrolytesas gate insulators,which enables a high gate capacitance per unit area (1–10 μFcm−2) due to the formation of electrical double layers (EDLs). Consequently, electrolyte-gated field-effect transistors (EGFETs) attain high-charge carrier densities already in the subvoltage regime, allowing for low-voltage operation of circuits and systems. This article presents a systematic study of lumped terminal capacitances of printed electrolyte-gated transistors under various dc bias conditions. We perform voltage-dependent impedancemeasurements and separate extrinsic components from the lumped terminal capacitance.
The proposed Meyer-like capacitance model, which also accounts for the nonquasi-static (NQS) effect, agrees well with experimental data. Finally, to verify the model, we implement it in Verilog-A and simulate the transient response of an inverter and a ring oscillator circuit. Simulation results are in good agreement with the measurement data of fabricated devices.
Advances in printed electronics (PE) enables new applications, particularly in ultra-low-cost domains. However, achieving high-throughput printing processes and manufacturing yield is one of the major challenges in the large-scale integration of PE technology. In this article, we present a programmable printed circuit based on an efficient printed lookup table (pLUT) to address these challenges by combining the advantages of the high-throughput advanced printing and maskless point-of-use final configuration printing. We propose a novel pLUT design which is more efficient in PE realization compared to existing LUT designs. The proposed pLUT design is simulated, fabricated, and programmed as different logic functions with inkjet printed conductive ink to prove that it can realize digital circuit functionality with the use of programmability features. The measurements show that the fabricated LUT design is operable at 1 V.
Printed electronics (PE) enables disruptive applications in wearables, smart sensors, and healthcare since it provides mechanical flexibility, low cost, and on-demand fabrication. The progress in PE raises trust issues in the supply chain and vulnerability to reverse engineering (RE) attacks. Recently, RE attacks on PE circuits have been successfully performed, pointing out the need for countermeasures against RE, such as camouflaging. In this article, we propose a printed camouflaged logic cell that can be inserted into PE circuits to thwart RE. The proposed cell is based on three components achieved by changing the fabrication process that exploits the additive manufacturing feature of PE. These components are optically look-alike, while their electrical behaviors are different, functioning as a transistor, short, and open. The properties of the proposed cell and standard PE cells are compared in terms of voltage swing, delay, power consumption, and area. Moreover, the proposed camouflaged cell is fabricated and characterized to prove its functionality. Furthermore, numerous camouflaged components are fabricated, and their (in)distinguishability is assessed to validate their optical similarities based on the recent RE attacks on PE. The results show that the proposed cell is a promising candidate to be utilized in camouflaging PE circuits with negligible overhead.
Printed electronics (PE) is a fast-growing field with promising applications in wearables, smart sensors, and smart cards, since it provides mechanical flexibility, and low-cost, on-demand, and customizable fabrication. To secure the operation of these applications, true random number generators (TRNGs) are required to generate unpredictable bits for cryptographic functions and padding. However, since the additive fabrication process of the PE circuits results in high intrinsic variations due to the random dispersion of the printed inks on the substrate, constructing a printed TRNG is challenging. In this article, we exploit the additive customizable fabrication feature of inkjet printing to design a TRNG based on electrolyte-gated field-effect transistors (EGFETs). We also propose a printed resistor tuning flow for the TRNG circuit to mitigate the overall process variation of the TRNG so that the generated bits are mostly based on the random noise in the circuit, providing a true random behavior. The simulation results show that the overall process variation of the TRNGs is mitigated by 110 times, and the generated bitstream of the tuned TRNGs passes the National Institute of Standards and Technology - Statistical Test Suite. For the proof of concept, the proposed TRNG circuit was fabricated and tuned. The characterization results of the tuned TRNGs prove that the TRNGs generate random bitstreams at the supply voltage of down to 0.5 V. Hence, the proposed TRNG design is suitable to secure low-power applications in this domain.
Printed electronics (PE) circuits have several advantages over silicon counterparts for the applications where mechanical flexibility, extremely low-cost, large area, and custom fabrication are required. The custom (personalized) fabrication is a key feature of this technology, enabling customization per application, even in small quantities due to low-cost printing compared with lithography. However, the personalized and on-demand fabrication, the non-standard circuit design, and the limited number of printing layers with larger geometries compared with traditional silicon chip manufacturing open doors for new and unique reverse engineering (RE) schemes for this technology. In this paper, we present a robust RE methodology based on supervised machine learning, starting from image acquisition all the way to netlist extraction. The results show that the proposed RE methodology can reverse engineer the PE circuits with very limited manual effort and is robust against non-standard circuit design, customized layouts, and high variations resulting from the inherent properties of PE manufacturing processes.
Printed electrolyte-gated oxide electronics is an emerging electronic technology in the low voltage regime (≤1 V). Whereas in the past mainly dielectrics have been used for gating the transistors, many recent approaches employ the advantages of solution processable, solid polymer electrolytes, or ion gels that provide high gate capacitances produced by a Helmholtz double layer, allowing for low-voltage operation. Herein, with special focus on work performed at KIT recent advances in building electronic circuits based on indium oxide, n-type electrolyte-gated field-effect transistors (EGFETs) are reviewed. When integrated into ring oscillator circuits a digital performance ranging from 250 Hz at 1 V up to 1 kHz is achieved. Sequential circuits such as memory cells are also demonstrated. More complex circuits are feasible but remain challenging also because of the high variability of the printed devices. However, the device inherent variability can be even exploited in security circuits such as physically unclonable functions (PUFs), which output a reliable and unique, device specific, digital response signal. As an overall advantage of the technology all the presented circuits can operate at very low supply voltages (0.6 V), which is crucial for low-power printed electronics applications.
In the domain of printed electronics (PE), field-effect transistors (FETs) with an oxide semiconductor channel are very promising. In particular, the use of high gate-capacitance of the composite solid polymer electrolytes (CSPEs) as a gate-insulator ensures extremely low voltage requirements. Besides high gate capacitance, such CSPEs are proven to be easily printable, stable in air over wide temperature ranges, and possess high ion conductivity. These CSPEs can be sensitive to moisture, especially for high surface-to-volume ratio printed thin films. In this paper, we provide a comprehensive experimental study on the effect of humidity on CSPE-gated single transistors. At the circuit level, the performance of ring oscillators (ROs) has been compared for various humidity conditions. The experimental results of the electrolyte-gated FETs (EGFETs) demonstrate rather comparable currents between 30%-90% humidity levels. However, the shifted transistor parameters lead to a significant performance change of the RO frequency behavior. The study in this paper shows the need of an impermeable encapsulation for the CSPE-gated FETs to ensure identical performance at all humidity conditions.
Oxide semiconductors have the potential to increase the performance of inkjet printed microelectronic devices such as field-effect transistors (FETs), due to their high electron mobilities. Typical metal oxides are n-type semiconductors, while p-type oxides, although realizable, exhibit lower carriermobilities. Therefore, the circuit design based on oxide semiconductors is mostly in n-type logic only. Here we present an inkjet printed pn-diode based on p- and n-type oxide semiconductors.Copper oxide or nickel oxide is used as p-typesemiconductor whereas n-typesemiconductor is realized with indium oxide. Themeasurements show that the pn-diodes operate in the voltage window typical for printed electronics and the emission coefficient is 1.505 and 2.199 for the copper oxide based and nickel oxidebased pn-diode, respectively.Furthermore, a pn-diode model is developed and integrable into a circuit simulator.
Electrolyte-gated thin-film transistors (EGTs) with indium oxide channel, and expected lifetime of three months, enable low-voltage operation (~1 V) in the field of printed electronics (PEs). The channel width of our printed EGTs is varied between 200 and 1000 μm, whereas a channel length between 10 and 100 μm is used. Due to the lack of uniform performance p-type metal oxide semiconductors, n-type EGTs and passive elements are used to design circuits. For logic gates, transistor-resistor logic has been employed so far, but depletion and enhancement-mode EGTs in a transistor-transistor logic boost the circuit performance in terms of delay and signal swing. In this article, the threshold voltage of the EGT, which determines the operation mode, is tuned through sizing of the EGTs channel geometry. The feasibility of both transistor operation modes is demonstrated for logic gates and ring oscillators. An inverter operating at a supply voltage of 1 V shows a maximum gain of 9.6 and a propagation delay time of 0.7 ms, which represents an improvement of ~ 2x for the gain and oscillation frequency, in comparison with the resistor-transistor logic design. Moreover, the power consumption is reduced by 6x.
An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications
(2018)
Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μm CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 mm2. The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μW. The analog part of the design consumes only 36 μW, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches.
Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface
(2018)
Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this paper, we present design details of a programmable passive SoC in compliance with ISO 15693/NFC5 standard for biomedical applications. The integrated system consists of a 32-bit microcontroller, a sensor readout circuit, a 12-bit SAR type ADC, 16 kB RAM, 16 kB ROM and other digital peripherals. The design is implemented in a 0.18 µm CMOS technology and used a die area of 1.52 mm × 3.24 mm. The simulated maximum power consumption of the analog block is 592 µW. The number of external components required by the SoC is limited to an external memory device, sensors, antenna and some passive components. The external memory device contains the application specific firmware. Based on the application, the firmware can be modified accordingly. The SoC design is suitable for medical implants to measure physiological parameters like temperature, pressure or ECG. As an application example, the authors have proposed a bioimplant to measure arterial blood pressure for patients suffering from Peripheral Artery Disease (PAD).