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Analysis of Miniaturized Printed Flexible RFID/NFC Antennas Using Different Carrier Substrates
(2020)
Antennas for Radio Frequency Identification (RFID) provide benefits for high frequencies (HF) and wireless data transmission via Near Field Communication (NFC) and many other applications. In this case, various requirements for the design of the reader and transmitter antennas must be met in order to achieve a suitable transmission quality. In this work, a miniaturized cost-effective RFID/NFC antenna for a microelectronic measurement system is designed and printed on different flexible carrier substrates using a new and low-cost Direct Ink Writing (DIW) technology. Various practical aspects such as reflection and impedance magnitude as well as the behavior of the printed RFID/NFC antennas are analyzed and compared to an identical copper-based antenna of the same size. The results are presented in this paper. Furthermore, the problems during the printing process itself on the different substrates are evaluated. The effects of the characteristics on the antenna under kink-free bending tests are examined and subsequently long-term measurements are carried out.
Purpose
This work presents a new monocular peer-to-peer tracking concept overcoming the distinction between tracking tools and tracked tools for optical navigation systems. A marker model concept based on marker triplets combined with a fast and robust algorithm for assigning image feature points to the corresponding markers of the tracker is introduced. Also included is a new and fast algorithm for pose estimation.
Methods
A peer-to-peer tracker consists of seven markers, which can be tracked by other peers, and one camera which is used to track the position and orientation of other peers. The special marker layout enables a fast and robust algorithm for assigning image feature points to the correct markers. The iterative pose estimation algorithm is based on point-to-line matching with Lagrange–Newton optimization and does not rely on initial guesses. Uniformly distributed quaternions in 4D (the vertices of a hexacosichora) are used as starting points and always provide the global minimum.
Results
Experiments have shown that the marker assignment algorithm robustly assigns image feature points to the correct markers even under challenging conditions. The pose estimation algorithm works fast, robustly and always finds the correct pose of the trackers. Image processing, marker assignment, and pose estimation for two trackers are handled in less than 18 ms on an Intel i7-6700 desktop computer at 3.4 GHz.
Conclusion
The new peer-to-peer tracking concept is a valuable approach to a decentralized navigation system that offers more freedom in the operating room while providing accurate, fast, and robust results.
Diffracted waves carry high‐resolution information that can help interpreting fine structural details at a scale smaller than the seismic wavelength. However, the diffraction energy tends to be weak compared to the reflected energy and is also sensitive to inaccuracies in the migration velocity, making the identification of its signal challenging. In this work, we present an innovative workflow to automatically detect scattering points in the migration dip angle domain using deep learning. By taking advantage of the different kinematic properties of reflected and diffracted waves, we separate the two types of signals by migrating the seismic amplitudes to dip angle gathers using prestack depth imaging in the local angle domain. Convolutional neural networks are a class of deep learning algorithms able to learn to extract spatial information about the data in order to identify its characteristics. They have now become the method of choice to solve supervised pattern recognition problems. In this work, we use wave equation modelling to create a large and diversified dataset of synthetic examples to train a network into identifying the probable position of scattering objects in the subsurface. After giving an intuitive introduction to diffraction imaging and deep learning and discussing some of the pitfalls of the methods, we evaluate the trained network on field data and demonstrate the validity and good generalization performance of our algorithm. We successfully identify with a high‐accuracy and high‐resolution diffraction points, including those which have a low signal to noise and reflection ratio. We also show how our method allows us to quickly scan through high dimensional data consisting of several versions of a dataset migrated with a range of velocities to overcome the strong effect of incorrect migration velocity on the diffraction signal.
Extracting horizon surfaces from key reflections in a seismic image is an important step of the interpretation process. Interpreting a reflection surface in a geologically complex area is a difficult and time-consuming task, and it requires an understanding of the 3D subsurface geometry. Common methods to help automate the process are based on tracking waveforms in a local window around manual picks. Those approaches often fail when the wavelet character lacks lateral continuity or when reflections are truncated by faults. We have formulated horizon picking as a multiclass segmentation problem and solved it by supervised training of a 3D convolutional neural network. We design an efficient architecture to analyze the data over multiple scales while keeping memory and computational needs to a practical level. To allow for uncertainties in the exact location of the reflections, we use a probabilistic formulation to express the horizons position. By using a masked loss function, we give interpreters flexibility when picking the training data. Our method allows experts to interactively improve the results of the picking by fine training the network in the more complex areas. We also determine how our algorithm can be used to extend horizons to the prestack domain by following reflections across offsets planes, even in the presence of residual moveout. We validate our approach on two field data sets and show that it yields accurate results on nontrivial reflectivity while being trained from a workable amount of manually picked data. Initial training of the network takes approximately 1 h, and the fine training and prediction on a large seismic volume take a minute at most.
Background: This paper presents a novel approach for a hand prosthesis consisting of a flexible, anthropomorphic, 3D-printed replacement hand combined with a commercially available motorized orthosis that allows gripping.
Methods: A 3D light scanner was used to produce a personalized replacement hand. The wrist of the replacement hand was printed of rigid material; the rest of the hand was printed of flexible material. A standard arm liner was used to enable the user’s arm stump to be connected to the replacement hand. With computer-aided design, two different concepts were developed for the scanned hand model: In the first concept, the replacement hand was attached to the arm liner with a screw. The second concept involved attaching with a commercially available fastening system; furthermore, a skeleton was designed that was located within the flexible part of the replacement hand.
Results: 3D-multi-material printing of the two different hands was unproblematic and inexpensive. The printed hands had approximately the weight of the real hand. When testing the replacement hands with the orthosis it was possible to prove a convincing everyday functionality. For example, it was possible to grip and lift a 1-L water bottle. In addition, a pen could be held, making writing possible.
Conclusions: This first proof-of-concept study encourages further testing with users.
Printed electronics (PE) enables disruptive applications in wearables, smart sensors, and healthcare since it provides mechanical flexibility, low cost, and on-demand fabrication. The progress in PE raises trust issues in the supply chain and vulnerability to reverse engineering (RE) attacks. Recently, RE attacks on PE circuits have been successfully performed, pointing out the need for countermeasures against RE, such as camouflaging. In this article, we propose a printed camouflaged logic cell that can be inserted into PE circuits to thwart RE. The proposed cell is based on three components achieved by changing the fabrication process that exploits the additive manufacturing feature of PE. These components are optically look-alike, while their electrical behaviors are different, functioning as a transistor, short, and open. The properties of the proposed cell and standard PE cells are compared in terms of voltage swing, delay, power consumption, and area. Moreover, the proposed camouflaged cell is fabricated and characterized to prove its functionality. Furthermore, numerous camouflaged components are fabricated, and their (in)distinguishability is assessed to validate their optical similarities based on the recent RE attacks on PE. The results show that the proposed cell is a promising candidate to be utilized in camouflaging PE circuits with negligible overhead.
Printed electronics (PE) is a fast-growing field with promising applications in wearables, smart sensors, and smart cards, since it provides mechanical flexibility, and low-cost, on-demand, and customizable fabrication. To secure the operation of these applications, true random number generators (TRNGs) are required to generate unpredictable bits for cryptographic functions and padding. However, since the additive fabrication process of the PE circuits results in high intrinsic variations due to the random dispersion of the printed inks on the substrate, constructing a printed TRNG is challenging. In this article, we exploit the additive customizable fabrication feature of inkjet printing to design a TRNG based on electrolyte-gated field-effect transistors (EGFETs). We also propose a printed resistor tuning flow for the TRNG circuit to mitigate the overall process variation of the TRNG so that the generated bits are mostly based on the random noise in the circuit, providing a true random behavior. The simulation results show that the overall process variation of the TRNGs is mitigated by 110 times, and the generated bitstream of the tuned TRNGs passes the National Institute of Standards and Technology - Statistical Test Suite. For the proof of concept, the proposed TRNG circuit was fabricated and tuned. The characterization results of the tuned TRNGs prove that the TRNGs generate random bitstreams at the supply voltage of down to 0.5 V. Hence, the proposed TRNG design is suitable to secure low-power applications in this domain.
Printed Electronics technology is a key-enabler for smart sensors, soft robotics, and wearables. The inkjet printed electrolyte-gated field effect transistor (EGFET) technology is a promising candidate for such applications due to its low-power operation, high field-effect mobility, and on-demand fabrication. Unlike conventional silicon-based technologies, inkjet printed electronics technology is an additive manufacturing process where multiple layers are printed on top of each other to realize functional devices such as transistors and their interconnections. Due to the additive manufacturing process, the technology has limited routing layers. For routing of complex circuits, insulating crossovers are printed at the intersection of routing paths to isolate them. The crossover can alter the electrical properties of a circuit based on specific location on a routing path. In this work, we propose a crossover-aware placement and routing (COPnR) methodology for inkjet-printed circuits by integrating the crossover constraints in our design framework. Our proposed placement methodology is based on a state-of-the-art evolutionary algorithm while the routing optimization is done using a genetic algorithm. The proposed methodology is compared with the industrial standard placement and routing (PnR) tools. On average, the proposed methodology has 38% fewer crossovers and 94% fewer failing paths compared to the industrial PnR tools applied to printed circuit designs.
Advances in printed electronics (PE) enables new applications, particularly in ultra-low-cost domains. However, achieving high-throughput printing processes and manufacturing yield is one of the major challenges in the large-scale integration of PE technology. In this article, we present a programmable printed circuit based on an efficient printed lookup table (pLUT) to address these challenges by combining the advantages of the high-throughput advanced printing and maskless point-of-use final configuration printing. We propose a novel pLUT design which is more efficient in PE realization compared to existing LUT designs. The proposed pLUT design is simulated, fabricated, and programmed as different logic functions with inkjet printed conductive ink to prove that it can realize digital circuit functionality with the use of programmability features. The measurements show that the fabricated LUT design is operable at 1 V.
High-performance Ag–Se-based n-type printed thermoelectric (TE) materials suitable for room-temperature applications have been developed through a new and facile synthesis approach. A high magnitude of the Seebeck coefficient up to 220 μV K–1 and a TE power factor larger than 500 μW m–1 K–2 for an n-type printed film are achieved. A high figure-of-merit ZT ∼0.6 for a printed material has been found in the film with a low in-plane thermal conductivity κF of ∼0.30 W m–1 K–1. Using this material for n-type legs, a flexible folded TE generator (flexTEG) of 13 thermocouples has been fabricated. The open-circuit voltage of the flexTEG for temperature differences of ΔT = 30 and 110 K is found to be 71.1 and 181.4 mV, respectively. Consequently, very high maximum output power densities pmax of 6.6 and 321 μW cm–2 are estimated for the temperature difference of ΔT = 30 K and ΔT = 110 K, respectively. The flexTEG has been demonstrated by wearing it on the lower wrist, which resulted in an output voltage of ∼72.2 mV for ΔT ≈ 30 K. Our results pave the way for widespread use in wearable devices.
Morphological transition of a rod-shaped phase into a string of spherical particles is commonly observed in the microstructures of alloys during solidification (Ratke and Mueller, 2006). This transition phenomenon can be explained by the classic Plateau-Rayleigh theory which was derived for fluid jets based on the surface area minimization principle. The quintessential work of Plateau-Rayleigh considers tiny perturbations (amplitude much less than the radius) to the continuous phase and for large amplitude perturbations, the breakup condition for the rod-shaped phase is still a knotty issue. Here, we present a concise thermodynamic model based on the surface area minimization principle as well as a non-linear stability analysis to generalize Plateau-Rayleigh’s criterion for finite amplitude perturbations. Our results demonstrate a breakup transition from a continuous phase via dispersed particles towards a uniform-radius cylinder, which has not been found previously, but is observed in our phase-field simulations. This new observation is attributed to a geometric constraint, which was overlooked in former studies. We anticipate that our results can provide further insights on microstructures with spherical particles and cylinder-shaped phases.
Amorphous In-Ga-Zn-O (IGZO) is a high-mobility semiconductor employed in modern thin-film transistors for displays and it is considered as a promising material for Schottky diode-based rectifiers. Properties of the electronic components based on IGZO strongly depend on the manufacturing parameters such as the oxygen partial pressure during IGZO sputtering and post-deposition thermal annealing. In this study, we investigate the combined effect of sputtering conditions of amorphous IGZO (In:Ga:Zn=1:1:1) and post-deposition thermal annealing on the properties of vertical thin-film Pt-IGZO-Cu Schottky diodes, and evaluated the applicability of the fabricated Schottky diodes for low-frequency half-wave rectifier circuits. The change of the oxygen content in the gas mixture from 1.64% to 6.25%, and post-deposition annealing is shown to increase the current rectification ratio from 10 5 to 10 7 at ±1 V, Schottky barrier height from 0.64 eV to 0.75 eV, and the ideality factor from 1.11 to 1.39. Half-wave rectifier circuits based on the fabricated Schottky diodes were simulated using parameters extracted from measured current-voltage and capacitance-voltage characteristics. The half-wave rectifier circuits were realized at 100 kHz and 300 kHz on as-fabricated Schottky diodes with active area of 200 μm × 200 μm, which is relevant for the near-field communication (125 kHz - 134 kHz), and provided the output voltage amplitude of 0.87 V for 2 V supply voltage. The simulation results matched with the measurement data, verifying the model accuracy for circuit level simulation.
Electrolyte-gated thin-film transistors (EGTs) with indium oxide channel, and expected lifetime of three months, enable low-voltage operation (~1 V) in the field of printed electronics (PEs). The channel width of our printed EGTs is varied between 200 and 1000 μm, whereas a channel length between 10 and 100 μm is used. Due to the lack of uniform performance p-type metal oxide semiconductors, n-type EGTs and passive elements are used to design circuits. For logic gates, transistor-resistor logic has been employed so far, but depletion and enhancement-mode EGTs in a transistor-transistor logic boost the circuit performance in terms of delay and signal swing. In this article, the threshold voltage of the EGT, which determines the operation mode, is tuned through sizing of the EGTs channel geometry. The feasibility of both transistor operation modes is demonstrated for logic gates and ring oscillators. An inverter operating at a supply voltage of 1 V shows a maximum gain of 9.6 and a propagation delay time of 0.7 ms, which represents an improvement of ~ 2x for the gain and oscillation frequency, in comparison with the resistor-transistor logic design. Moreover, the power consumption is reduced by 6x.
Fully Printed Inverters using Metal‐Oxide Semiconductor and Graphene Passives on Flexible Substrates
(2020)
Printed and flexible metal‐oxide transistor technology has recently demonstrated great promise due to its high performance and robust mechanical stability. Herein, fully printed inverter structures using electrolyte‐gated oxide transistors on a flexible polyimide (PI) substrate are discussed in detail. Conductive graphene ink is printed as the passive structures and interconnects. The additive printed transistors on PI substrates show an on/off ratio of 106 and show mobilities similar to the state‐of‐the‐art printed transistors on rigid substrates. Printed meander structures of graphene are used as pull‐up resistances in a transistor–resistor logic to create fully printed inverters. The printed and flexible inverters show a signal gain of 3.5 and a propagation delay of 30 ms. These printed inverters are able to withstand a tensile strain of 1.5% following more than 200 cycles of mechanical bending. The stability of the electrical direct current (DC) properties has been observed over a period of 5 weeks. These oxide transistor‐based fully printed inverters are relevant for digital printing methods which could be implemented into roll‐to‐roll processes.
In this report, we have studied field-effect transistors (FETs) using low-density alumina for electrolytic gating. Device layers have been prepared starting from the structured ITO glasses by printing the In 2 O 3 channels, low-temperature atomic layer deposition (ALD) of alumina (Al 2 O 3 ), and printing graphene top gates. The transistor performance could be deliberately changed by alternating the ambient humidity; furthermore, ID,ON/ID,OFF-ratios of up to seven orders of magnitude and threshold voltages between 0.66 and 0.43 V, decreasing with an increasing relative humidity between 40% and 90%, could be achieved. In contrast to the common usage of Al 2 O 3 as the dielectric in the FETs, our devices show electrolyte-typegating behavior. This is a result from the formation of protons on the Al 2 O 3 surfaces at higher humidities. Due to the very high local capacitances of the Helmholtz double layers at the channel surfaces, the operation voltage can be as low as 1 V. At low humidities (≤30%), the solid electrolyte dries out and the performance breaks down; however, it can fully reversibly be regained upon a humidity increase. Using ALD-derived alumina as solid electrolyte gating material, thus, allows low-voltage operation and provides a chemically stable gating material while maintaining low process temperatures. However, it has proven to be highly humidity-dependent in its performance.
In this study, a facile method to fabricate a cohesive ion‐gel based gate insulator for electrolyte‐gated transistors is introduced. The adhesive and flexible ion‐gel can be laminated easily on the semiconducting channel and electrode manually by hand. The ion‐gel is synthesized by a straightforward technique without complex procedures and shows a remarkable ionic conductivity of 4.8 mS cm−1 at room temperature. When used as a gate insulator in electrolyte‐gated transistors (EGTs), an on/off current ratio of 2.24×104 and a subthreshold swing of 117 mV dec−1 can be achieved. This performance is roughly equivalent to that of ink drop‐casted ion‐gels in electrolyte‐gated transistors, indicating that the film‐attachment method might represent a valuable alternative to ink drop‐casting for the fabrication of gate insulators.
Rectifiersare vital electronic circuits for signal and power conversion in various smart sensor applications. The ability to process low input voltage levels, for example, from vibrational energy harvesters is a major challenge with existing passive rectifiers in printed electronics, stemming mainly from the built-in potential of the diode's p-njunction. To address this problem, in this work, we design, fabricate, and characterize an inkjet-printed full-wave rectifier using diode-connected electrolyte-gated thin-film transistors (EGTs). Using both experimental and simulation approaches, we investigate how the rectifier can benefit from the near-zero threshold voltage of transistors, which can be enabled by proper channel geometry setting in EGT technology. The presented circuit can be operated at 1-V input voltage, featuring a remarkably small voltage loss of 140 mV and a cutoff frequency of ~300 Hz. Below the cutoff frequency, more than 2.6-μW dc power is obtained over the load resistances ranging from 5 to 20 kQ. Furthermore, experiments show that the circuit can work with an input amplitude down to 500 mV. This feature makes the presented design highly suitable for a variety of energy-harvesting applications.
Hybrid low-voltage physical unclonable function based on inkjet-printed metal-oxide transistors
(2020)
Modern society is striving for digital connectivity that demands information security. As an emerging technology, printed electronics is a key enabler for novel device types with free form factors, customizability, and the potential for large-area fabrication while being seamlessly integrated into our everyday environment. At present, information security is mainly based on software algorithms that use pseudo random numbers. In this regard, hardware-intrinsic security primitives, such as physical unclonable functions, are very promising to provide inherent security features comparable to biometrical data. Device-specific, random intrinsic variations are exploited to generate unique secure identifiers. Here, we introduce a hybrid physical unclonable function, combining silicon and printed electronics technologies, based on metal oxide thin film devices. Our system exploits the inherent randomness of printed materials due to surface roughness, film morphology and the resulting electrical characteristics. The security primitive provides high intrinsic variation, is non-volatile, scalable and exhibits nearly ideal uniqueness.
Diese Arbeit beschäftigt sich mit der Biomechanik der Halswirbelsäule (HWS) beim Umgang mit dem Smartphone. Die Kräfte, die auf Wirbelkörper, Wirbelgelenke, Bandscheiben, Muskeln und Bänder wirken, werden mit steigendem Flexionswinkel der HWS größer. Die Beschwerden hingegen, welche der Smartphone-Nacken hervorruft, sind meist akut und mit regelmäßiger Bewegung und der Stärkung der Nackenmuskulatur gut zu behandeln. Eine Therapie ist somit auch zur Vorbeugung geeignet. Doch die Langzeitauswirkungen sind nicht außer Acht zu lassen, denn durch die steigenden Nutzungsmöglichkeiten der Smartphones steigt auch der durchschnittliche tägliche Gebrauch stärker an. So wird vor allem die tägliche Bildschirmzeit bei Jugendlichen immer länger. Das aktuell noch akute Krankheitsbild des Smartphone-Nackens, das nur selten einen chronischen Verlauf nimmt und Langzeitschäden verursacht, könnte sich durch fehlende oder zu späte Maßnahmen zu einem größeren chronischen Krankheitsbild entwickeln.
A disturbed synchronization of the ventricular contraction can cause a highly developed systolic heart failure in affected patients with reduction of the left ventricular ejection fraction, which can often be explained by a diseased left bundle branch block (LBBB). If medication remains unresponsive, the concerned patients will be treated with a cardiac resynchronization therapy (CRT) system. The aim of this study was to integrate His-bundle pacing into the Offenburg heart rhythm model in order to visualize the electrical pacing field generated by His-Bundle-Pacing. Modelling and electrical field simulation activities were performed with the software CST (Computer Simulation Technology) from Dessault Systèms. CRT with biventricular pacing is to be achieved by an apical right ventricular electrode and an additional left ventricular electrode, which is floated into the coronary vein sinus. The non-responder rate of the CRT therapy is about one third of the CRT patients. His- Bundle-Pacing represents a physiological alternative to conventional cardiac pacing and cardiac resynchronization. An electrode implanted in the His-bundle emits a stronger electrical pacing field than the electrical pacing field of conventional cardiac pacemakers. The pacing of the Hisbundle was performed by the Medtronic Select Secure 3830 electrode with pacing voltage amplitudes of 3 V, 2 V and 1,5 V in combination with a pacing pulse duration of 1 ms. Compared to conventional pacemaker pacing, His-bundle pacing is capable of bridging LBBB conduction disorders in the left ventricle. The His-bundle pacing electrical field is able to spread via the physiological pathway in the right and left ventricles for CRT with a narrow QRS-complex in the surface ECG.