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Im Institut für angewandte Forschung (IAF) der FH Offenburg wird derzeit eine Chipkarte entwickelt, mit der Temperaturzeitreihen über längere Zeiträume aufgezeichnet werden können. Die zur Datenerfassung erforderlichen Systemkomponenten sind auf nur einem Halbleiterchip zusammengefaßt, wodurch sich bei großen Produktionsstückzahlen ein sehr niedriger Herstellpreis erzielen läßt. Die 'Thermologger' genannte Chipkarte kann zudem mit Standard-Chipkartenlesern und einer dedizierten Software auf jedem PC konfiguriert, gelesen und ausgewertet werden.
Formal verification (FV) is considered by many to be complicated and to require considerable mathematical knowledge for successful application. We have developed a methodology in which we have added formal verification to the verification process without requiring any knowledge of formal verification languages. We use only finite-state machine notation, which is familiar and intuitive to designers. Another problem associated with formal verification is state-space explosion. If that occurs, no result is returned; our method switches to random simulation after one hour without results, and no effort is lost. We have compared FV against random simulation with respect to development time, and our results indicate that FV is at least as fast as random simulation. FV is superior in terms of verification quality, however, because it is exhaustive.
The flow field-flow fractionation (FIFFF) technique is a promising method for separating and analysing particles and large size macromolecules from a few nanometers to approximately 50 μm. A new fractionation channel is described featuring well defined flow conditions even for low channel heights with convenient assembling and operations features. The application of the new flow field-flow fractionation channel is proved by the analysis of pigments and other small particles of technical interest in the submicrometer range. The experimental results including multimodal size distributions are presented and discussed.