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RETIS – Real-Time Sensitive Wireless Communication Solution for Industrial Control Applications
(2020)
Ultra-Reliable Low Latency Communications (URLLC) has been always a vital component of many industrial applications. The paper proposes a new wireless URLLC solution called RETIS, which is suitable for factory automation and fast process control applications, where low latency, low jitter, and high data exchange rates are mandatory. In the paper, we describe the communication protocol as well as the hardware structure of the network nodes for implementing the required functionality. Many techniques enabling fast, reliable wireless transmissions are used – short Transmission Time Interval (TTI), Time-Division Multiple Access (TDMA), MIMO, optional duplicated data transfer, Forward Error Correction (FEC), ACK mechanism. Preliminary tests show that reliable end-to-end latency down to 350 μs and packet exchange rate up to 4 kHz can be reached (using quadruple MIMO and standard IEEE 802.15.4 PHY at 250 kbit/s).
Unterschiedliche Stimulationszeitpunkte bei bimodaler Versorgung mit Hörgerät und Cochleaimplantat
(2023)
Die bimodale Versorgung von Patienten mit Hörgerät (HG) ipsilateral und Cochleaimplantat (CI) kontralateral bei asymmetrischem Hörverlust ist aufgrund vieler inhärenter Variablen die komplizierteste Versorgungsart im Kontext der Versorgung mit CI. Im vorliegenden Übersichtsartikel werden alle systematischen interauralen Unterschiede zwischen elektrischer und akustischer Stimulation dargestellt, die bei dieser Versorgungsart auftreten können. Darüber hinaus werden Methoden zur Quantifizierung des interauralen Latenzoffsets, also des Zeitunterschieds zwischen der akustischen und elektrischen Stimulation des Hörnervs, mittels Registrierung auditorisch evozierter Potenziale – erzeugt durch akustische bzw. elektrische Stimulation – und Messungen an den Sprachprozessoren und Hörgeräten vorgestellt. Die technische Kompensation des interauralen Latenzoffsets und ihre positive Auswirkung auf die Schalllokalisationsfähigkeit bimodal mit CI und HG versorgter Patienten wird ebenfalls beschrieben. Zuletzt werden neueste Erkenntnisse diskutiert, die Gründe dafür aufzeigen, warum die Kompensation des interauralen Latenzoffsets das Sprachverstehen im Störgeräusch bei bimodal versorgten CI-/HG-Trägern nicht verbessert.
In bimodal cochlear implant (CI) / hearing aid (HA) users a constant interaural time delay in the order of several milliseconds occurs due to differences in signal processing of the devices. For MED-EL CI systems in combination with different HA types, we have quantified the respective device delay mismatch (Zirn et al. 2015). In the current study, we investigate the effect of the device delay mismatch in simulated and actual bimodal listeners on sound localization accuracy.
To deal with the device delay mismatch in actual bimodal listeners we delayed the CI stimulation according to the measured HA processing delay and two other values. With all delay values highly significant improvements of the rms error in the localization task were observed compared to the test without the delay. The results help to narrow down the optimal patient-specific delay value.
Zeitliche Anpassung führt zu verbesserter Schalllokalisation bei bimodal versorgten CI-/HG-Trägern
(2021)
Bei bimodal versorgten Cochlea-Implantaten (CI) / Hörgerät (HG)-Trägern entsteht durch die unterschiedliche Signalverarbeitung der Geräte eine konstante interaurale Zeitverzögerung in der Größenordnung von mehreren Millisekunden. Für MED-EL CI-Systeme in Kombination mit verschiedenen HG-Typen haben wir den jeweiligen Device-Delay-Mismatch quantifiziert. In der aktuellen Studie untersuchen wir den Einfluss der Device-Delay-Mismatch bei simulierten und tatsächlichen bimodalen Hörern auf die Genauigkeit der Schalllokalisation.
Um den Device-Delay-Mismatch bei bimodal versorgten Patienten zu verringern, haben wir die CI-Stimulation um die gemessene HG-Signallaufzeit und zwei weitere Werte verzögert. Nach einer Angewöhnungsphase war der effektive Winkelfehler bei Verzögerung um die HG-Signallaufzeit hochsignifikant reduziert im Vergleich zu der Testkondition ohne CI-Verzögerung (mittlere Verbesserung: 11 % ; p < .01, Wilcoxon Signed Rank Test). Aber auch mit den beiden weiteren Verzögerungswerten wurden Verbesserungen erreicht. Anhand der Ergebnisse lässt sich der optimale patientenspezifische Verzögerungswert näher eingrenzen.
In users of a cochlear implant (CI) together with a contralateral hearing aid (HA), so-called bimodal listeners, differences in processing latencies between digital HA and CI up to 9 ms constantly superimpose interaural time differences. In the present study, the effect of this device delay mismatch on sound localization accuracy was investigated. For this purpose, localization accuracy in the frontal horizontal plane was measured with the original and minimized device delay mismatch. The reduction was achieved by delaying the CI stimulation according to the delay of the individually worn HA. For this, a portable, programmable, battery-powered delay line based on a ring buffer running on a microcontroller was designed and assembled. After an acclimatization period to the delayed CI stimulation of 1 hr, the nine bimodal study participants showed a highly significant improvement in localization accuracy of 11.6% compared with the everyday situation without the delay line (p < .01). Concluding, delaying CI stimulation to minimize the device delay mismatch seems to be a promising method to increase sound localization accuracy in bimodal listeners.
In dieser Arbeit wird der Bildbearbeitungsprozess von Dokumenten mithilfe von einem schlicht gehaltenem Neuronalen Netzwerk und Bearbeitungsoperationen optimiert. Ziel ist es, abfotografierte Dokumente zum Drucken aufzubereiten, sodass die Schrift gut lesbar, gerade und nicht verzerrt ist und Störfaktoren herausgefiltert werden. Als API zur Verfügung gestellt, können Bilder von Dokumenten beliebiger Größe und Schriftgröße bearbeitet werden. Während ein unter schlechten Bedingungen schräg aufgenommenes Bild nach Tesseract keine Buchstaben enthält, wird mit dem bearbeiteten Bild davon eine Buchstabenfehlerrate von 0,9% erreicht.
Novel manufacturing technologies, such as printed electronics, may enable future applications for the Internet of Everything like large-area sensor devices, disposable security, and identification tags. Printed physically unclonable functions (PUFs) are promising candidates to be embedded as hardware security keys into lightweight identification devices. We investigate hybrid PUFs based on a printed PUF core. The statistics on the intra- and inter-hamming distance distributions indicate a performance suitable for identification purposes. Our evaluations are based on statistical simulations of the PUF core circuit and the thereof generated challenge-response pairs. The analysis shows that hardware-intrinsic security features can be realized with printed lightweight devices.
A physical unclonable function (PUF) is a hardware circuit that produces a random sequence based on its manufacturing-induced intrinsic characteristics. In the past decade, silicon-based PUFs have been extensively studied as a security primitive for identification and authentication. The emerging field of printed electronics (PE) enables novel application fields in the scope of the Internet of Things (IoT) and smart sensors. In this paper, we design and evaluate a printed differential circuit PUF (DiffC-PUF). The simulation data are verified by Monte Carlo analysis. Our design is highly scalable while consisting of a low number of printed transistors. Furthermore, we investigate the best operating point by varying the PUF challenge configuration and analyzing the PUF security metrics in order to achieve high robustness. At the best operating point, the results show areliability of 98.37% and a uniqueness of 50.02%, respectively. This analysis also provides useful and comprehensive insights into the design of hybrid or fully printed PUF circuits. In addition, the proposed printed DiffC-PUF core has been fabricated with electrolyte-gated field-effect transistor technology to verify our design in hardware.
Modern society is more than ever striving for digital connectivity -- everywhere and at any time, giving rise to megatrends such as the Internet of Things (IoT). Already today, 'things' communicate and interact autonomously with each other and are managed in networks. In the future, people, data, and things will be interlinked, which is also referred to as the Internet of Everything (IoE). Billions of devices will be ubiquitously present in our everyday environment and are being connected over the Internet.
As an emerging technology, printed electronics (PE) is a key enabler for the IoE offering novel device types with free form factors, new materials, and a wide range of substrates that can be flexible, transparent, as well as biodegradable. Furthermore, PE enables new degrees of freedom in circuit customizability, cost-efficiency as well as large-area fabrication at the point of use.
These unique features of PE complement conventional silicon-based technologies. Additive manufacturing processes enable the realization of many envisioned applications such as smart objects, flexible displays, wearables in health care, green electronics, to name but a few.
From the perspective of the IoE, interconnecting billions of heterogeneous devices and systems is one of the major challenges to be solved. Complex high-performance devices interact with highly specialized lightweight electronic devices, such as e.g. smartphones and smart sensors. Data is often measured, stored, and shared continuously with neighboring devices or in the cloud. Thereby, the abundance of data being collected and processed raises privacy and security concerns.
Conventional cryptographic operations are typically based on deterministic algorithms requiring high circuit and system complexity, which makes them unsuitable for lightweight devices.
Many applications do exist, where strong cryptographic operations are not required, such as e.g. in device identification and authentication. Thereby, the security level mainly depends on the quality of the entropy source and the trustworthiness of the derived keys. Statistical properties such as the uniqueness of the keys are of great importance to precisely distinguish between single entities.
In the past decades, hardware-intrinsic security, particularly physically unclonable functions (PUFs), gained a lot of attraction to provide security features for IoT devices. PUFs use their inherent variations to derive device-specific unique identifiers, comparable to fingerprints in biometry.
The potentials of this technology include the use of a true source of randomness, on demand key derivation, as well as inherent key storage.
Combining these potentials with the unique features of PE technology opens up new opportunities to bring security to lightweight electronic devices and systems. Although PE is still far from being matured and from being as reliable as silicon technology, in this thesis we show that PE-based PUFs are promising candidates to provide key derivation suitable for device identification in the IoE.
Thereby, this thesis is primarily concerned with the development, investigation, and assessment of PE-based PUFs to provide security functionalities to resource constrained printed devices and systems.
As a first contribution of this thesis, we introduce the scalable PE-based Differential Circuit PUF (DiffC-PUF) design to provide secure keys to be used in security applications for resource constrained printed devices. The DiffC-PUF is designed as a hybrid system architecture incorporating silicon-based and inkjet-printed components. We develop an embedded PUF platform to enable large-scale characterization of silicon and printed PUF cores.
In the second contribution of this thesis, we fabricate silicon PUF cores based on discrete components and perform statistical tests under realistic operating conditions. A comprehensive experimental analysis on the PUF security metrics is carried out. The results show that the silicon-based DiffC-PUF exhibits nearly ideal values for the uniqueness and reliability metrics. Furthermore, the identification capabilities of the DiffC-PUF are investigated and it is shown that additional post-processing can further improve the quality of the identification system.
In the third contribution of this thesis, we firstly introduce an evaluation workflow to simulate PE-based DiffC-PUFs, also called hybrid PUFs. Hereof, we introduce a Python-based simulation environment to investigate the characteristics and variations of printed PUF cores based on Monte Carlo (MC) simulations. The simulation results show, that the security metrics to be expected from the fabricated devices are close to ideal at the best operating point.
Secondly, we employ fabricated printed PUF cores for statistical tests under varying operating conditions including variations in ambient temperature, relative humidity, and supply voltage. The evaluations of the uniqueness, bit aliasing, and uniformity metrics are in good agreement with the simulation results. The experimentally determined mean reliability value is relatively low, which can be explained by the missing passivation and encapsulation of the printed transistors. The investigation of the identification capabilities based on the raw PUF responses shows that the pure hybrid PUF is not suitable for cryptographic applications, but qualifies for device identification tasks.
The final contribution is to switch to the perspective of an attacker. To judge on the security capabilities of the hybrid PUF, a comprehensive security analysis in the manner of a cryptanalysis is performed. The analysis of the entropy of the hybrid PUF shows that its vulnerability against model-based attacks mainly depends on the selected challenge building method. Furthermore, an attack methodology is introduced to assess the performances of different mathematical cloning attacks on the basis of eavesdropped challenge-response pairs (CRPs). To clone the hybrid PUF, a sorting algorithm is introduced and compared with commonly used supervised machine learning (ML) classifiers including logistic regression (LR), random forest (RF), as well as multi-layer perceptron (MLP).
The results show that the hybrid PUF is vulnerable against model-based attacks. The sorting algorithm benefits from shorter training times compared to the ML algorithms. If the eavesdropped CRPs are erroneous, the ML algorithms outperform the sorting algorithm.
Für die Prognose von Zeitreihen sind bezüglich der Qualität der Vorhersagen heutzutage neuronale Netze und Deep Learning das Mittel der Wahl. LSTM-Netzwerke etablierten sich dazu als eine gut funktionierende Herangehensweise. 2017 wurde der auf Attention basierende Transformer für die Übersetzung von Sprache vorgestellt. Aufgrund seiner Fähigkeit mit sequenziellen Daten zu arbeiten, ist er auch für Zeitreihenprobleme interessant. Diese wissenschaftliche Arbeit befasst sich mit der Vorhersage von Zeitreihen mit einem Transformer. Es wird analysiert, inwiefern sich ein Transformer für Zeitreihenvorhersagen von einem Transformer für Sprachübersetzungen unterscheidet und wie gut die Vorhersagen im Vergleich zu denen eines LSTM-Netzwerkes abschneiden. Dazu werden ein LSTM- und ein Transformer-Netzwerk auf Luftqualitäts- und Wetterdaten in Berlin trainiert, um den Feinstaubgehalt (PM25) in der Luft vorherzusagen. Die Ergebnisse werden mit einem Benchmark-Modell anhand von Evaluationsmetriken verglichen. Anschließend wird evaluiert, wie die Fehler des Transformers reduziert werden können und wie gut der Transformer generalisiert.
Narrowband Internet-of-Things (NB-IoT) is a 3rd generation partnership project (3GPP) standardized cellular technology, adopted for 5G and optimized for massive Machine Type Communication (mMTC). Applications are anticipated around infrastructure monitoring, asset management, smart city and smart energy applications. In this paper, we evaluate the suitability of NB-IoT for private (campus) networks in industrial environments, including complex cloud-based applications around process automation. An end-to-end system has been developed, comprising of a sensor unit connected to a NB-IoT modem, a base station (gNodeB) equipped with a beamforming array and a local (private) network architecture comprising a sensor management system in the edge cloud. The experimental study includes field tests in realistic industrial environments with latency, reliability and coverage measurements. The results show a good suitability of NB-IoT for process automation with high scalability, low-power requirements and moderate latency requirements.
The development of Internet of Things (IoT) embedded devices is proliferating, especially in the smart home automation system. However, the devices unfortunately are imposing overhead on the IoT network. Thus, the Internet Engineering Task Force (IETF) have introduced the IPv6 Low-Power Wireless Personal Area Network (6LoWPAN) to provide a solution to this constraint. 6LoWPAN is an Internet Protocol (IP) based communication where it allows each device to connect to the Internet directly. As a result, the power consumption is reduced. However, the limitation of data transmission frame size of the IPv6 Routing Protocol for Low-power and Lossy Network’s (RPL’s) had made it to be the running overhead, and thus consequently degrades the performance of the network in terms of Quality of Service (QoS), especially in a large network. Therefore, HRPL was developed to enhance the RPL protocol to minimize redundant retransmission that causes the routing overhead. We introduced the T-Cut Off Delay to set the limit of the delay and the H field to respond to actions taken within the T-Cut Off Delay. Thus, this paper presents the comparison performance assessment of HRPL between simulation and real-world scenarios (6LoWPAN Smart Home System (6LoSH) testbed) in validating the HRPL functionalities. Our results show that HRPL had successfully reduced the routing overhead when implemented in 6LoSH. The observed Control Traffic Overhead (CTO) packet difference between each experiment is 7.1%, and the convergence time is 9.3%. Further research is recommended to be conducted for these metrics: latency, Packet Delivery Ratio (PDR), and throughput.
The Internet of Things (IoT) application has becoming progressively in-demand, most notably for the embedded devices (ED). However, each device has its own difference in computational capabilities, memory usage, and energy resources in connecting to the Internet by using Wireless Sensor Networks (WSNs). In order for this to be achievable, the WSNs that form the bulk of the IoT implementation requires a new set of technologies and protocol that would have a defined area, in which it addresses. Thus, IPv6 Low Power Area Network (6LoWPAN) was designed by the Internet Engineering Task Force (IETF) as a standard network for ED. Nevertheless, the communication between ED and 6LoWPAN requires appropriate routing protocols for it to achieve the efficient Quality of Service (QoS). Among the protocols of 6LoWPAN network, RPL is considered to be the best protocol, however its Energy Consumption (EC) and Routing Overhead (RO) is considerably high when it is implemented in a large network. Therefore, this paper would propose the HRPL to enchance the RPL protocol in reducing the EC and RO. In this study, the researchers would present the performance of RPL and HRPL in terms of EC, Control traffic Overhead (CTO) and latency based on the simulation of the 6LoWPAN network in fixed environment using COOJA simulator. The results show HRPL protocol achieves better performance in all the tested topology in terms of EC and CTO. However, the latency of HRPL only improves in chain topology compared with RPL. We found that further research is required to study the relationship between the latency and the load of packet transmission in order to optimize the EC usage.
Extensible Authentication Protocol (EAP) bietet eine flexible Möglichkeit zur Authentifizierung von Endgeräten und kann in Kombination mit TLS für eine zertifikatsbasierte Authentifizierung verwendet werden. Motiviert wird diese Arbeit von einer potenziellen Erweiterung für PROFINET, die diese Protokolle einsetzen soll.
Dabei soll eine sicherer EAP-TLS-Protokollstacks für eingebettete Systeme in der Programmiersprache Rust entwickelt werden. Durch das Ownership-System von Rust können Speicherfehler eliminiert werden, ohne dabei auf die positiven Eigenschaften von nativen Sprachen zu verzichten. Es wird ein besonderes Augenmerk auf wie die Verwendung klassischer Rust-Bibliotheken im Umfeld von eingebetteten Systemen, den Einfluss des Speichermodells auf das Design, sowie die Integration von C-Bibliotheken für automatisierte Interoperabilitätstests gelegt.
Das Messstellenbetriebsgesetz sieht bis 2032 einen Pflichteinbau von modernen Messeinrichtungen bzw. intelligenten Messsystemen bei allen Verbrauchern und Erzeugern vor. Des Weiteren ist die Anbindung von regenerativen Erzeugungsanlagen und steuerbaren Verbrauchern sowie die netzdienliche Steuerung dieser Einrichtungen über das Smart Meter Gateway durch das Messstellenbetriebsgesetz vorgeschrieben. Diese netzdienliche Steuerung wird unter dem Begriff CLS-Management zusammengefasst und muss von allen Netzbetreibern und Messstellenbetreibern künftig umgesetzt werden. Im Rahmen der Bachelorarbeit wurde ein Testaufbau mit einem intelligenten Messsystem inklusive entsprechender Steuereinrichtung aufgebaut, um das CLS-Management an einfachen Schalthandlungen zu erproben. Die daraus gewonnenen Erfahrungen sollen dem Messstellenbetreiber dabei helfen, das Thema in der Wirkumgebung platzieren zu können. Ziel dieses Aufbaus ist es, über die Kommunikationsart LTE eine Schalthandlung an einer Steuerbox in der Rolle des externen Marktteilnehmers vornehmen zu können. Für die Umsetzung wird eine entsprechende Software des Gateway Herstellers zur Verfügung gestellt, um die Versuche außerhalb des zertifizierten Bereiches durch-führen zu können.
Als konkreten Anwendungsfall wird im Rahmen der Thesis die Ablösung der Funkrundsteuertechnik durch das CLS-Management betrachtet. Mit dem Rollout der intelligenten Messsystemen müssen künftig die steuerbaren Verbrauchseinrichtungen und regenerativen Erzeugungsanlagen über das Smart Meter Gateway gesteuert werden können. Dies hat gegenüber der Funkrundsteuertechnik den entscheidenden Vorteil, dass die Informationen über eine gesicherte TLS-Verbindungen übertragen werden und durch einen Rückkanal auch Informationen über das korrekte Ausführung der Schalthandlung beim externen Marktteilnehmer ankommen.
Als weiteren Anwendungsfall wird untersucht, wie über ein Smart Meter Gateway außer Steuersignale auch Energiedaten und Sollwerte von externen Marktteilnehmer an Smart Grid Infrastrukturen übertragen werden können, um diese optimal betreiben zu können. Als Grundlage dient hierfür das Micro Grid am INES der Hochschule Offenburg
Neuromorphic computing systems have demonstrated many advantages for popular classification problems with significantly less computational resources. We present in this paper the design, fabrication and training of a programmable neuromorphic circuit, which is based on printed electrolytegated field-effect transistor (EGFET). Based on printable neuron architecture involving several resistors and one transistor, the proposed circuit can realize multiply-add and activation functions. The functionality of the circuit, i.e. the weights of the neural network, can be set during a post-fabrication step in form of printing resistors to the crossbar. Besides the fabrication of a programmable neuron, we also provide a learning algorithm, tailored to the requirements of the technology and the proposed programmable neuron design, which is verified through simulations. The proposed neuromorphic circuit operates at 5V and occupies 385mm 2 of area.
In many application domains, in particular automotives, guaranteeing a very low failure rate is crucial to meet functional and safety standards. Especially, reliable operation of memory components such as SRAM cells is of essential importance. Due to aggressive technology downscaling, process and runtime variations significantly impact manufacturing yield as well as functionality. For this reason, a thorough memory failure rate assessment is imperative for correct circuit operation and yield improvement. In this regard, Monte Carlo simulations have been used as the conventional method to estimate the variability induced failure rate of memory components. However, Monte Carlo methods become infeasible when estimating rare events such as high-sigma failure rates. To this end, Importance Sampling methods have been proposed which reduce the number of required simulations substantially. However, existing methods still suffer from inaccuracies and high computational efforts, in particular for high-sigma problems. In this paper, we fill this gap by presenting an efficient mixture Importance Sampling approach based on Bayesian optimization, which deploys a surface model of the objective function to find the most probable failure points. Its advantages include constant complexity independent of the dimensions of design space, the potential to find the global extrema, and higher trustworthiness of the estimated failure rate by accurately exploring the design space. The approach is evaluated on a 6T-SRAM cell as well as a master-slave latch based on a 28nm FDSOI process. The results show an improvement in accuracy, resulting in up to 63× better accuracy in estimating failure rates compared to the best state-of-the-art solutions on a 28nm technology node.
Emerging applications in soft robotics, wearables, smart consumer products or IoT-devices benefit from soft materials, flexible substrates in conjunction with electronic functionality. Due to high production costs and conformity restrictions, rigid silicon technologies do not meet application requirements in these new domains. However, whenever signal processing becomes too comprehensive, silicon technology must be used for the high-performance computing unit. At the same time, designing everything in flexible or printed electronics using conventional digital logic is not feasible yet due to the limitations of printed technologies in terms of performance, power and integration density. We propose to rather use the strengths of neuromorphic computing architectures consisting in their homogeneous topologies, few building blocks and analog signal processing to be mapped to an inkjet-printed hardware architecture. It has remained a challenge to demonstrate non-linear elements besides weighted aggregation. We demonstrate in this work printed hardware building blocks such as inverter-based comprehensive weight representation and resistive crossbars as well as printed transistor-based activation functions. In addition, we present a learning algorithm developed to train the proposed printed NCS architecture based on specific requirements and constraints of the technology.