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With the expansion of IoT devices in many aspects of our life, the security of such systems has become an important challenge. Unlike conventional computer systems, any IoT security solution should consider the constraints of these systems such as computational capability, memory, connectivity, and power consumption limitations. Physical Unclonable Functions (PUFs) with their special characteristics were introduced to satisfy the security needs while respecting the mentioned constraints. They exploit the uncontrollable and reproducible variations of the underlying component for security applications such as identification, authentication, and communication security. Since IoT devices are typically low cost, it is important to reuse existing elements in their hardware (for instance sensors, ADCs, etc.) instead of adding extra costs for the PUF hardware. Micro-electromechanical system (MEMS) devices are widely used in IoT systems as sensors and actuators. In this thesis, a comprehensive study of the potential application of MEMS devices as PUF primitives is provided. MEMS PUF leverages the uncontrollable variations in the parameters of MEMS elements to derive secure keys for cryptographic applications. Experimental and simulation results show that our proposed MEMS PUFs are capable of generating enough entropy for a complex key generation, while their responses show low fluctuations in different environmental conditions.
Keeping in mind that the PUF responses are prone to change in the presence of noise and environmental variations, it is critical to derive reliable keys from the PUF and to use the maximum entropy at the same time. In the second part of this thesis, we elaborate on different key generation schemes and their advantages and drawbacks. We propose the PUF output positioning (POP) and integer linear programming (ILP) methods, which are novel methods for grouping the PUF outputs in order to maximize the extracted entropy. To implement these methods, the key enrollment and key generation algorithms are presented. The proposed methods are then evaluated by applying on the responses of the MEMS PUF, where it can be practically shown that the proposed method outperforms other existing PUF key generation methods.
The final part of this thesis is dedicated to the application of the MEMS PUF as a security solution for IoT systems. We select the mutual authentication of IoT devices and their backend system, and propose two lightweight authentication protocols based on MEMS PUFs. The presented protocols undergo a comprehensive security analysis to show their eligibility to be used in IoT systems. As the result, the output of this thesis is a lightweight security solution based on MEMS PUFs, which introduces a very low overhead on the cost of the hardware.
Die Erfindung betrifft ein Verfahren zum Maximieren der von einer analogen Entropiequelle abgeleiteten Entropie, wobei das Verfahren folgende Schritte aufweist:- Bereitstellen von Eingabedaten für die analoge Entropiequelle (2);- Erzeugen von Rückgabewerten durch die analoge Entropiequelle basierend auf den Eingabedaten (3); und- Gruppieren der Rückgabewerte, wobei das Gruppieren der Rückgabewerte ein Anwenden von Versätzen auf Rückgabewerte aufweist (4).
MINT-College TIEFE
(2021)
Das Projekt MINT-College TIEFE konnte in der zweiten Förderperiode die verschiedenen Maßnahmen der vorangegangenen Förderperiode weiter ausbauen und verstetigen. Die Angebote im Rahmen des Projekts MINT-College TIEFE begleiteten die Studierenden über den Student-Life-Cycle hinweg über das komplette Studium der technischen Studiengänge, beginnend in der Schule und endend beim Übergang in den Beruf. Um die Qualität der Lehre an der Hochschule Offenburg zu verbessern, wurden darüber hinaus verschiedene digital unterstützte Lehrformate weiterentwickelt und ausgebaut. Zentrale Angebote des MINT-College, das 2019 zentrale Einrichtung der Hochschule Offenburg wurde, sind die für die Studieneingangsphase entwickelten Angebote der Einführungstage, des Mentorenprogramms, der Brückenkurse, des Lernzentrums und Angebote für den Übergang in den Beruf, wie das Gründerbüro. Die mediendidaktischen Unterstützungsangebote für Lehrende unterstützten den Lernkulturwandel an der Hochschule. Es wurden systematisch nachhaltige Strukturen aufgebaut, um Innovationen für das Lehren und das Lernen auch künftig entwickeln, erproben und etablieren zu können.
Bei bimodaler Cochlea-Implantat-/Hörgerät-Versorgung kann es aufgrund seitenverschiedener Signalverarbeitung zu einer zeitlich versetzten Stimulation der beiden Modalitäten kommen. Jüngste Studien haben gezeigt, dass durch zeitlichen Abgleich der Modalitäten die Schalllokalisation bei bimodaler Versorgung verbessert werden kann. Um solch einen Abgleich vornehmen zu können, ist die messtechnische Bestimmung der Durchlaufzeit von Hörgeräten erforderlich. Kommerziell verfügbare Hörgerätemessboxen können diese Werte häufig liefern. Die dazu verwendete Signalverarbeitung wird dabei aber oft nicht vollständig offengelegt. In dieser Arbeit wird ein alternativer und nachvollziehbarer Ansatz zum Design eines simplen Messaufbaus basierend auf einem Arduino DUE Mikrocontroller-Board vorgestellt. Hierzu wurde ein Messtisch im 3D-Druck gefertigt, auf welchem Hörgeräte über einen 2-ccm-Kuppler an ein Messmikrofon angeschlossen werden können. Über einen Latenzvergleich mit dem simultan erfassten Signal eines Referenzmikrofons kann die Durchlaufzeit von Hörgeräten bestimmt werden. Frequenzspezifische Durchlaufzeiten werden mittels einer Kreuzkorrelation zwischen Ziel- und Referenzsignal errechnet. Aufnahme, Ausgabe und Speicherung der Signale erfolgt über einen ATMEL SAM3X8E Mikrocontroller, welcher auf dem Arduino DUE-Board verbaut ist. Über eigens entworfene elektronische Schaltungen werden die Mikrofone und der verwendete Lautsprecher angesteuert. Nach Abschluss einer Messung (Messdauer ca. 5 s) werden die Messdaten seriell an einen PC übertragen, auf dem die Datenauswertung mittels MATLAB erfolgt. Erste Validierungen zeigten eine hohe Stabilität der Messergebnisse mit sehr geringen Standardabweichungen im Bereich weniger Mikrosekunden für Pegel zwischen 50 und 75 dB (A). Der Messaufbau wird in laufenden Studien zur Quantifizierung der Durchlaufzeit von Hörgeräten verwendet.
Modelbasierte Zustandsschätzung elektrischer Betriebsmittel der Mittel- und Niederspannungsebenen
(2022)
Im Projekt MOBCOM wird ein neues Verfahren zur Zustandsüberwachung von elektrischen Betriebsmitteln in Niederspannungsnetzen und Anlagen entwickelt. Mittels PLC (power line communication) Technologie werden hochfrequente transiente Vorgänge auf dem Stromkanal und dessen Übertragungseigenschaften erfasst und bewertet.
In dem Abschlussbericht wird ein Prototyp für Powerline-Kommunikation zur Netzüberwachung beschrieben. Der Prototyp basiert auf einem PLC-Empfänger, welcher den Kanal misst, um so Informationen über den PLC-Kanal und den aktuellen Zustand des Stromnetzes zu erhaltet. Der PLC-Empfänger verwendet das Kommunikationssignal, um eine genaue Schätzung des Stromkanals zu erhalten und liefert Informationen zur Erkennung von Teilentladungen und anderen Anomalien im Netz. Diese Überwachung des Stromnetzes macht sich die bestehende PLC-Infrastruktur zunutze und verwendet die ohnehin übertragenen Datensignale, um eine Echtzeitmessung der Kanalübertragungsfunktion und des empfangenen Rauschsignals zu erhalten. Da dieses Signal im Vergleich zu einfacheren Messsensoren mit einer hohen Abtastrate abgetastet wird, enthält es wertvolle Informationen über mögliche Beeinträchtigungen im Netz, die behoben werden müssen. Während die Kanalmessungen auf einem empfangenen PLC-Signal beruhen, können Informationen über Teilentladungen oder andere Störquellen allein durch einen PLC-Empfänger gesammelt werden, d. h. ohne eine PLC-Übertragung. Es wurde ein Prototyp auf Basis von Software Defined Radio entwickelt, der die gleichzeitige Kommunikation und Erfassung für ein Stromnetz implementiert.
Ultra-low-power passive telemetry systems for industrial and biomedical applications have gained much popularity lately. The reduction of the power consumption and size of the circuits poses critical challenges in ultra-low-power circuit design. Biotelemetry applications like leakage detection in silicone breast implants require low-power-consuming small-size electronics. In this doctoral thesis, the design, simulation, and measurement of a programmable mixed-signal System-on-Chip (SoC) called General Application Passive Sensor Integrated Circuit (GAPSIC) is presented. Owing to the low power consumption, GAPSIC is capable of completely passive operation. Such a batteryless passive system has lower maintenance complexity and is also free from battery-related health hazards. With a die area of 4.92 mm² and a maximum analog power consumption of 592 µW, GAPSIC has one of the best figure-of-merits compared to similar state-of-the-art SoCs. Regarding possible applications, GAPSIC can read out and digitally transmit the signals of resistive sensors for pressure or temperature measurements. Additionally, GAPSIC can measure electrocardiogram (ECG) signals and conductivity.
The design of GAPSIC complies with the International Organization for Standardization (ISO) 15693/NFC (near field communication) 5 standard for radio frequency identification (RFID), corresponding to the frequency range of 13.56 MHz. A passive transponder developed with GAPSIC comprises of an external memory storage and very few other external components, like an antenna and sensors. The passive tag antenna and reader antenna use inductive coupling for communication and energy transfer, which enables passive operation. A passive tag developed with GAPSIC can communicate with an NFC compatible smart device or an ISO 15693 RFID reader. An external memory storage contains the programmable application-specific firmware.
As a mixed-signal SoC, GAPSIC includes both analog and digital circuitries. The analog block of GAPSIC includes a power management unit, an RFID/NFC communication unit, and a sensor readout unit. The digital block includes an integrated 32-bit microcontroller, developed by the Hochschule Offenburg ASIC design center, and digital peripherals. A 16-kilobyte random-access memory and a read-only 16-kilobyte memory constitute the GAPSIC internal memory. For the fabrication of GAPSIC, one poly, six-metal 0.18 µm CMOS process is used.
The design of GAPSIC includes two stages. In the first stage, a standalone RFID/NFC frontend chip with a power management unit, an RFID/NFC communication unit, a clock regenerator unit, and a field detector unit was designed. In the second stage, the rest of the functional blocks were integrated with the blocks of the RFID/NFC frontend chip for the final integration of GAPSIC. To reduce the power consumption, conventional low-power design techniques were applied extensively like multiple power supplies, and the operation of complementary metal-oxide-semiconductor (CMOS) transistors in the sub-threshold region of operation, as well as further innovative circuit designs.
An overvoltage protection circuit, a power rectifier, a bandgap reference circuit, and two low-dropout (LDO) voltage regulators constitute the power management unit of GAPSIC. The overvoltage protection circuit uses a novel method where three stacked transistor pairs shunt the extra voltage. In the power rectifier, four rectifier units are arranged in parallel, which is a unique approach. The four parallel rectifier units provide the optimal choice in terms of voltage drop and the area required.
The communication unit is responsible for RFID/NFC communication and incorporates demodulation and load modulation circuitry. The demodulator circuit comprises of an envelope detector, a high-pass filter, and a comparator. Following a new approach, the bandgap reference circuit itself acts as the load for the envelope detector circuit, which minimizes the circuit complexity and area. For the communication between the reader and the RFID/NFC tag, amplitude-shift keying (ASK) is used to modulate signals, where the smallest modulation index can be as low as 10%. A novel technique involving a comparator with a preset offset voltage effectively demodulates the ASK signal. With an effective die area of 0.7 mm² and power consumption of 107 µW, the standalone RFID/NFC frontend chip has the best figure-of-merits compared to the state-of-the-art frontend chips reported in the relevant literature. A passive RFID/NFC tag developed with the standalone frontend chip, as well as temperature and pressure sensors demonstrate the full passive operational capability of the frontend chip. An NFC reader device using a custom-built Android-based application software reads out the sensor data from the passive tag.
The sensor readout circuit consists of a channel selector with two differential and four single-ended inputs with a programmable-gain instrumentation amplifier. The entire sensor readout part remains deactivated when not in use. The internal memory stores the measured offset voltage of the instrumentation amplifier, where a firmware code removes the offset voltage from the measured sensor signal. A 12-bit successive approximation register (SAR) type analog-to-digital-converter (ADC) based on a charge redistribution architecture converts the measured sensor data to a digital value. The digital peripherals include a serial peripheral interface, four timers, RFID/NFC interfaces, sensor readout unit interfaces, and 12-bit SAR logic.
Two sets of studies with custom-made NFC tag antennas for biomedical applications were conducted to ascertain their compatibility with GAPSIC. The first study involved the link efficiency measurements of NFC tag antennas and an NFC reader antenna with porcine tissue. In a separate experiment, the effect of a ferrite compared to air core on the antenna-coupling factor was investigated. With the ferrite core, the coupling factor increased by four times.
Among the state-of-the-art SoCs published in recent scientific articles, GAPSIC is the only passive programmable SoC with a power management unit, an RFID/NFC communication interface, a sensor readout circuit, a 12-bit SAR ADC, and an integrated 32-bit microcontroller. This doctoral research includes the preliminary study of three passive RFID tags designed with discrete components for biomedical and industrial applications like measurements of temperature, pH, conductivity, and oxygen concentration, along with leakage detection in silicone breast implants. Besides its small size and low power consumption, GAPSIC is suitable for each of the biomedical and industrial applications mentioned above due to the integrated high-performance microcontroller, the robust programmable instrumentation amplifier, and the 12-bit analog-to-digital converter. Furthermore, the simulation and measurement data show that GAPSIC is well suited for the design of a passive tag to monitor arterial blood pressure in patients experiencing Peripheral Artery Disease (PAD), which is proposed in this doctoral thesis as an exemplary application of the developed system.
Team description papers of magmaOffenburg are incremental in the sense that each year we address a different topic of our team and the tools around our team. In this year’s team description paper we focus on the architecture of the software. It is a main factor for being able to keep the code maintainable even after 15 years of development. We also describe how we make sure that the code follows this architecture.
This paper presents the new Deep Reinforcement Learning (DRL) library RL-X and its application to the RoboCup Soccer Simulation 3D League and classic DRL benchmarks. RL-X provides a flexible and easy-to-extend codebase with self-contained single directory algorithms. Through the fast JAX-based implementations, RL-X can reach up to 4.5x speedups compared to well-known frameworks like Stable-Baselines3.
Herzfehler sind weltweit die häufigste Form von angeborenen Organdefekten. In unterschiedlichen Studien wird die Inzidenz zumeist zwischen vier und elf von 1.000 Lebendgeburten angegeben (1–5). Im Rahmen der multizentrischen PAN-Studie (PAN: Prävalenz angeborener Herzfehler bei Neugeborenen), welche die Häufigkeit angeborener Herzfehler bei Neugeborenen in Deutschland zwischen Juli 2006 und Juni 2007 untersuchte, ergab sich eine Gesamtprävalenz von 107,6 pro 10.000 Lebendgeburten. Gegenstand dieser Arbeit sind Untersuchungen an Implantaten zur Behandlung von Atriumseptumdefekten (ASD). Vorhofseptumdefekte machen mit 17,0%, nach den Ventrikelseptumdefekten (VSD) mit 48,9%die zweithäufigste Art von Herzfehlern aus (6, 7).Als Vorhofseptumdefekte werden Öffnungen in der Scheidewand zwischen den Herzvorhöfen bezeichnet. Bei der Therapie eines ASD ist der minimalinvasive Verschluss mittels sogenannter Okkluder heute das Mittel der Wahl. Diese werden über einen femoralen Zugang im Rahmen einer Herzkatheteruntersuchung unter Ultraschallkontrolle und Durchleuchtung an die Implantationsstelle vorgeschoben und dort platziert(8). Die Okkluder bestehen in der Regel aus einem Drahtgeflecht aus Nitinol und haben die typische Form eines sogenannten Doppelschirmchens. Dabei weichen die unterschiedlichen Okkluder der einzelnen Firmen hinsichtlich Form und Beschaffenheit oft erheblich voneinander ab. Derzeit gibt es keine Untersuchungsmethode, die die auf dem Markt befindlichen Okkluder hinsichtlich ihrer mechanischen Eigenschaften vergleichbar macht. Diese Arbeit solleinen Beitrag erbringen, um grundlegende, die Okkludermodelle charakterisierende Parameter zu schaffen, um so deren interindividuelle Vergleichbarkeit zu ermöglichen. Hierzu werden in-vitro Messungen durchgeführt, welche geeignet sind das Verhalten der untersuchten Modelle unter unterschiedlichen Bedingungen und bei variierenden Defektgrößen zu charakterisieren.
Die Erfindung betrifft eine Schaltungsanordnung (10) für ein Kraftfahrzeug, mit einer Hochvolt-Batterie (12) zum Speichern von elektrischer Energie, mit wenigstens einer elektrischen Maschine (14) zum Antreiben des Kraftfahrzeugs, mit einem Stromrichter (16), mittels welchem von der Hochvolt-Batterie (12) bereitstellbare Hochvolt-Gleichspannung in Hochvolt-Wechselspannung zum Betreiben der elektrischen Maschine (14) umwandelbar ist, und mit einem Ladeanschluss (20) zum Bereitstellen von elektrischer Energie zum Laden der Hochvolt-Batterie (12), wobei der Stromrichter (16) als ein Drei-Stufen-Stromrichter ausgebildet ist und wenigstens eine einer Phase (u) der elektrischen Maschine (14) zugeordnete Schaltereinheit (46) aufweist, welche zwei in Reihe geschaltete Schaltergruppen (52, 54) umfasst, die jeweils zwei in Reihe geschaltete IGBTs (T11, T12, T13, T14) aufweisen, wobei zwischen den IGBTs (T11, T12) einer der Schaltergruppen (52, 54) ein Anschluss (64) angeordnet ist, welcher direkt mit einer Leitung (34) des Ladeanschlusses (20) elektrisch verbunden ist.
A circuit arrangement of a motor vehicle includes a high-voltage battery for storing electrical energy, an electric machine for driving the motor vehicle, a converter via which high-voltage direct current voltage provided by the high-voltage battery is convertible into high-voltage alternating current voltage for operating the electric machine, and a charging connection for providing electrical energy for charging the high-voltage battery. The converter is a three-stage converter having a first switch unit which is assigned to a first phase of the electric machine. The first switch unit has two switch groups connected in series which each have two insulated-gate bipolar transistors (IGBTs) connected in series, where a connection is disposed between the IGBTs of one of the two switch groups, which connection is electrically connected directly to a line of the charging connection.
Printed electrolyte-gated oxide electronics is an emerging electronic technology in the low voltage regime (≤1 V). Whereas in the past mainly dielectrics have been used for gating the transistors, many recent approaches employ the advantages of solution processable, solid polymer electrolytes, or ion gels that provide high gate capacitances produced by a Helmholtz double layer, allowing for low-voltage operation. Herein, with special focus on work performed at KIT recent advances in building electronic circuits based on indium oxide, n-type electrolyte-gated field-effect transistors (EGFETs) are reviewed. When integrated into ring oscillator circuits a digital performance ranging from 250 Hz at 1 V up to 1 kHz is achieved. Sequential circuits such as memory cells are also demonstrated. More complex circuits are feasible but remain challenging also because of the high variability of the printed devices. However, the device inherent variability can be even exploited in security circuits such as physically unclonable functions (PUFs), which output a reliable and unique, device specific, digital response signal. As an overall advantage of the technology all the presented circuits can operate at very low supply voltages (0.6 V), which is crucial for low-power printed electronics applications.
Due to its performance, the field of deep learning has gained a lot of attention, with neural networks succeeding in areas like Computer Vision (CV), Neural Language Processing (NLP), and Reinforcement Learning (RL). However, high accuracy comes at a computational cost as larger networks require longer training time and no longer fit onto a single GPU. To reduce training costs, researchers are looking into the dynamics of different optimizers, in order to find ways to make training more efficient. Resource requirements can be limited by reducing model size during training or designing more efficient models that improve accuracy without increasing network size.
This thesis combines eigenvalue computation and high-dimensional loss surface visualization to study different optimizers and deep neural network models. Eigenvectors of different eigenvalues are computed, and the loss landscape and optimizer trajectory are projected onto the plane spanned by those eigenvectors. A new parallelization method for the stochastic Lanczos method is introduced, resulting in faster computation and thus enabling high-resolution videos of the trajectory and secondorder information during neural network training. Additionally, the thesis presents the loss landscape between two minima along with the eigenvalue density spectrum at intermediate points for the first time.
Secondly, this thesis presents a regularization method for Generative Adversarial Networks (GANs) that uses second-order information. The gradient during training is modified by subtracting the eigenvector direction of the biggest eigenvalue, preventing the network from falling into the steepest minima and avoiding mode collapse. The thesis also shows the full eigenvalue density spectra of GANs during training.
Thirdly, this thesis introduces ProxSGD, a proximal algorithm for neural network training that guarantees convergence to a stationary point and unifies multiple popular optimizers. Proximal gradients are used to find a closed-form solution to the problem of training neural networks with smooth and non-smooth regularizations, resulting in better sparsity and more efficient optimization. Experiments show that ProxSGD can find sparser networks while reaching the same accuracy as popular optimizers.
Lastly, this thesis unifies sparsity and neural architecture search (NAS) through the framework of group sparsity. Group sparsity is achieved through ℓ2,1-regularization during training, allowing for filter and operation pruning to reduce model size with minimal sacrifice in accuracy. By grouping multiple operations together, group sparsity can be used for NAS as well. This approach is shown to be more robust while still achieving competitive accuracies compared to state-of-the-art methods
In this paper, we propose a unified approach for network pruning and one-shot neural architecture search (NAS) via group sparsity. We first show that group sparsity via the recent Proximal Stochastic Gradient Descent (ProxSGD) algorithm achieves new state-of-the-art results for filter pruning. Then, we extend this approach to operation pruning, directly yielding a gradient-based NAS method based on group sparsity. Compared to existing gradient-based algorithms such as DARTS, the advantages of this new group sparsity approach are threefold. Firstly, instead of a costly bilevel optimization problem, we formulate the NAS problem as a single-level optimization problem, which can be optimally and efficiently solved using ProxSGD with convergence guarantees. Secondly, due to the operation-level sparsity, discretizing the network architecture by pruning less important operations can be safely done without any performance degradation. Thirdly, the proposed approach finds architectures that are both stable and well-performing on a variety of search spaces and datasets.
We demonstrate how to exploit group sparsity in order to bridge the areas of network pruning and neural architecture search (NAS). This results in a new one-shot NAS optimizer that casts the problem as a single-level optimization problem and does not suffer any performance degradation from discretizating the architecture.