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HPTLC (High Performance Thin Layer Chromatography) is a well known and versatile separation method which shows many advantages when compared to other separation techniques. The method is fast and inexpensive and does not need time-consuming pretreatments. For visualisation of the sample distribution on a HPTLC-plate we developed a new and sturdy HPTLC-scanner. The scanner allows simultaneous registrations of spectra in a range from 198 nm to 612 nm with a spectral resolution of better than 0.8 nm. The on-plate spatial resolution is better than 160 μm. The measurement of 450 spectra in one separation track does not need more than two minutes. The new diode-array scanner offers a fast survey over a TLC-separation and makes various chemometric applications possible. For compound identification a cross-correlation function is described to compare UV sample spectra with appropriate library data. The cross-correlation function herein described can also be used for purity testing. Unresolved peaks can be virtually separated by use of a least squares fit algorithm. In summary, the diode arry system delivers much more information than the commonly used TLC-scanner.
Wireless communication systems more and more become part of our daily live. Especially with the Internet of Things (IoT) the overall connectivity increases rapidly since everyday objects become part of the global network. For this purpose several new wireless protocols have arisen, whereas 6LoWPAN (IPv6 over Low power Wireless Personal Area Networks) can be seen as one of the most important protocols within this sector. Originally designed on top of the IEEE802.15.4 standard it is a subject to various adaptions that will allow to use 6LoWPAN over different technologies; e.g. DECT Ultra Low Energy (ULE). Although this high connectivity offers a lot of new possibilities, there are several requirements and pitfalls coming along with such new systems. With an increasing number of connected devices the interoperability between different providers is one of the biggest challenges, which makes it necessary to verify the functionality and stability of the devices and the network. Therefore testing becomes one of the key components that decides on success or failure of such a system. Although there are several protocol implementations commonly available; e.g., for IoT based systems, there is still a lack of according tools and environments as well as for functional and conformance testing. This article describes the architecture and functioning of the proposed test framework based on Testing and Test Control Notation Version 3 (TTCN-3) for 6LoWPAN over ULE networks.
Training deep neural networks using backpropagation is very memory and computationally intensive. This makes it difficult to run on-device learning or fine-tune neural networks on tiny, embedded devices such as low-power micro-controller units (MCUs). Sparse backpropagation algorithms try to reduce the computational load of on-device learning by training only a subset of the weights and biases. Existing approaches use a static number of weights to train. A poor choice of this so-called backpropagation ratio limits either the computational gain or can lead to severe accuracy losses. In this paper we present TinyProp, the first sparse backpropagation method that dynamically adapts the back-propagation ratio during on-device training for each training step. TinyProp induces a small calculation overhead to sort the elements of the gradient, which does not significantly impact the computational gains. TinyProp works particularly well on fine-tuning trained networks on MCUs, which is a typical use case for embedded applications. For typical datasets from three datasets MNIST, DCASE2020 and CIFAR10, we are 5 times faster compared to non-sparse training with an accuracy loss of on average 1%. On average, TinyProp is 2.9 times faster than existing, static sparse backpropagation algorithms and the accuracy loss is reduced on average by 6 % compared to a typical static setting of the back-propagation ratio.
Time Resolved Measurements of Soot Concentrations and Mean Particle Sizes during EUDC and ECE Cycles
(2002)
Turbocharger housings in internal combustion engines are subjected to severe mechanical and thermal cyclic loads throughout their life-time or during engine testing. The combination of thermal transients and mechanical load cycling results in a complex evolution of damage, leading to thermo-mechanical fatigue (TMF) of the material. For the computational TMF life assessment of high temperature components, the DTMF model can provide reliable TMF life predictions. The model is based on a short fatigue crack growth law and uses local finite-element (FE) results to predict the number of cycles to failure for a technical crack. In engine applications, it is nowadays often acceptable to have short cracks as long as they do not propagate and cause loss of function of the component. Thus, it is necessary to predict not only potential crack locations and the corresponding number of cycles for a technical crack, but also to determine subsequent crack growth or even a possible crack arrest. In this work, a method is proposed that allows the simulation of TMF crack growth in high temperature components using FE simulations and non-linear fracture mechanics (NLFM).
A NLFM based crack growth simulation method is described. This method starts with the FE analysis of a component. In this paper, the method is demonstrated for an automotive turbocharger housing subjected to TMF loading. A transient elastic-viscoplastic FE analysis is used to simulate four heating and cooling cycles of an engine test. The stresses, inelastic strains, and temperature histories from the FEA are then used to perform TMF life predictions using the standard DTMF model. The crack position and the crack plane of critical hotspots are then identified. Simulated cracks are inserted at the hotspots. For the model demonstrated, cracks were inserted at two hotspot locations. The ΔJ integral is computed as a fracture mechanics parameter at each point along the crack-front, and the crack extension of each point is then evaluated, allowing the crack to grow iteratively. The paper concludes with a comparison of the crack growth curves for both hotspots with experimental results.
Nach dem Nachweis der Funktionalität des an der Fachhochschule Offenburg entwickelten Mikroprozessorkernels FHOP (First Homemade Operational Processor), wird eine Anwendung des Kernels in einem Applikationschip beschrieben.
Der Thermologger-ASIC soll mit Hilfe eines Temperatursensors die Umgebungstemperatur bei technischen Prozessen in regelmäßigen Zeitabständen erfassen und abspeichern. Die Meßwerte werden bei Bedarf ber eine serielle Schnittstelle des Thermologger-ASICs an einen PC übertragen und ausgewertet. Zur Verringerung der Leistungsaufnahme wird zwischen zwei Temperaturmessungen in einen Power-Down-Mode geschaltet.
Der ASIC soll später in einer Chipkarte integriert werden.
Im Institut für angewandte Forschung (IAF) der FH Offenburg wird derzeit eine Chipkarte entwickelt, mit der Temperaturzeitreihen über längere Zeiträume aufgezeichnet werden können. Die zur Datenerfassung erforderlichen Systemkomponenten sind auf nur einem Halbleiterchip zusammengefaßt, wodurch sich bei großen Produktionsstückzahlen ein sehr niedriger Herstellpreis erzielen läßt. Die 'Thermologger' genannte Chipkarte kann zudem mit Standard-Chipkartenlesern und einer dedizierten Software auf jedem PC konfiguriert, gelesen und ausgewertet werden.
Die zunehmende Anzahl von Transistoren mit immer kleineren Strukturgrößen führt zu einer zunehmenden Leistungsaufnahme in modernen Prozessoren. Das gilt insbesondere für High-End Prozessoren, die mit einer hohen Taktfrequenz betrieben werden. Die aufgenommene Leistung wird in Wärme umgewandelt, die in einer Temperaturerhöhung der Prozessoren resultiert. Hohe Betriebstemperaturen verursachen u.a. eine verringerte Rechenleistung, eine kürzere Lebensdauer des Prozessors und höhere Leckströme. Aus diesen Gründen wird aktives, dynamisches thermisches Management immer wichtiger. Dieser Beitrag stellt eine Erweiterung zu dem Standard- Linux-Scheduler in der Kernel-Version 3.0 für eingebettete Systeme vor: einen PID-Regler, der unter Angabe einer Solltemperatur eine dynamische Frequenz- und Spannungsskalierung durchführt. Die Experimente auf dem Freescale LMX6 Quadcore-Prozessor zeigen, dass der PID-Regler die Betriebstemperatur des Prozessors an die Solltemperatur regeln kann. Er ist die Grundlage für eine in Zukunft zu entwickelnde prädiktive Regelung.